2

ICS9248-61

Pin Descriptions

Pin number

Pin name

Type

Description

2

X1

Input

14.318 MHz crystal input

3

X2

Output

14.318 MHz crystal output

4

PCICLK_F

Output

3.3 V free running PCI clock output, will not be stopped by the PCI_STOP#

7

GNDPCI

Power

Ground for PCI clock outputs

8

VDDPCI

Power

3.3 V power for the PCI clock outputs

12

PCICLK_E

Output

Early PCICLK output, offset from other PCICLKs, stopped by PCI-STOP#

13

VDD48

Power

3.3 V power for 48 MHz clocks

14

SEL 100_66#/

48MHz

Input

on power-on control for the frequency of clocks at the CPU & PCICLK output pins. If

logic "0" is used the 66.6 MHz frequency is selected. If Logic "1" is used, the 100

MHz frequency is selected. The PCI clock is multiplexed to run at 33.3 MHz for both

selects

15

GND48

Power

Ground for 48 MHz clocks

16

DIV4#

Input

Active low input, enables the CPUCLK and the PCICLK to run at 1/4 of the regular

frequecies

17

PD#

Input

Asynchronous active low input pin used to power down the device into a low power

state. The internal clocks are disabled and the VCO and the crystal are stopped. The

latency of the power down will not be greater than 3ms.

18

CPU_STOP#

Input

Asynchronous active low input pin used to stop the CPUCLK in active low state, all

other clocks will continue to run. The CPUCLK will have a "Turnon " latency of at

least 3 CPU clocks.

19

VDDCOR

Input

3.3 V power for the core

20

PCI-STOP#

Input

Synchronous active low input used to stop the PCICLK in active low state. It will not

effect PCICLK_F or any other outputs.

21

GNDR/C

Input

Ground for REFCLK, Crystal & Core

22

GNDLCPU

Power

Ground for the CPU and Host clock outputs

25

VDDLCPU

Power

2.5 V power for the CPU and Host clock outputs

26

SPREAD#

Output

power-on spread spectrum enable option. Active low = spread spectrum clocking

enable. Active high = spread spectrum clocking disable.

28

VDDR

Input

3.3 V power for the REFCLK and crystal clock outputs

1,27

REF(0:1)

Output

3.3V, 14.318 MHz reference clock output.

23,24

CPUCLK (0:1)

0utput

2.5 V CPU and Host clock outputs

5,6,9,10, 11

PCICLK (1:4)

Output

3.3 V PCI clock outputs, generating timing requirements