Integrated

Circuit

Systems, Inc.

ICS9248-65

Third party brands and names are the property of their respective owners.

Block Diagram

9248-65 Rev C 7/28/99

Pin Configuration

48-pin SSOP

-3 CPUclocks(2.5V,100/133MHz)

- 10 PCI clocks, including 1 free-running

(3.3V, 33.3MHz)

-1CPU/2clocks(2.5V,50/66.6MHz)

-1IOAPICclocks(2.5V,16.67MHz)

- 3 Fixed frequency 66MHz clocks(3.3V, 66.6MHz)

- 2REFclocks(3.3V,14.318MHz)

- 1USBclock(3.3V,48MHz)

IOAPIC, 3V66 and CPU/2 output clocks.

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any

information being relied upon by the customer is current and accurate.

Features

Key Specification

•

CPU Output Jitter: <250ps

•

CPU/2 Output Jitter. <250ps

•

IOAPIC Output Jitter: <500ps

•

48MHz, 3V66, PCI Output Jitter: <500ps

•

PCI Output Jitter. <500ps

•

Ref Output Jitter. <1000ps

•

CPU 0:2 Output Skew: <175ps

•

PCI_F, PCI 1:7 Output Skew: <500ps

•

3V66_0:2 Output Skew <250ps

•

CPU to 3V66_0:2 Output Offset: 0.0 - 1.5ns (CPU leads)

•

3V66 to PCI Output Offset: 1.5 - 4ns (CPU leads)

•

CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads)