Integrated

Circuit

Systems, Inc.

ICS9248-87

Third party brands and names are the property of their respective owners.

Block Diagram

9248-87 Rev D 10/27/00

Recommended Application:

810/810E type chipset.

Output Features:

•

2- CPUs @2.5V, up to 155MHz.

•

9 - SDRAM @ 3.3V, up to 155MHz.

•

8 - PCICLK @ 3.3V

•

1 - IOAPIC @ 2.5V,

•

2 - 3V66MHz @ 3.3V

•

2- 48MHz, @3.3V fixed.

•

1- 24/48MHz, @3.3V

•

1- REF @3.3V, 14.318MHz.

Features:

•

Up to 155MHz frequency support

•

Support FS0-FS3 strapping status bit for I

•

Support power management: Power down Mode from I

programming.

•

Spread spectrum for EMI control ( ± 0.25% center).

•

Uses external 14.318MHz crystal

Skew Specifications:

•

CPU – CPU: <175ps

•

SDRAM - SDRAM: < 250ps

•

3V66 – 3V66: <175ps

•

PCI – PCI: <500ps

•

For group skew specification, please refer to group

timing relationships table.

Preliminary Product Preview

Functionality

Pin Configuration

48-Pin 300mil SSOP

*: These inputs have a 120K pull up to VDD.

1: These are double strength.

3

S

F2

S

F1

S

F0

S

F

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4

2

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17

6

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2

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3

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1

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2

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0

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6

40

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2

.

2

23

5

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4

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11

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6

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3

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10

8

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6

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4

.

3

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7

.

6

10

4

.

3

3

Frequency Generator & Integrated Buffers for Celeron & PII/III™

SEL24_48#

PLL2

PLL1

Spread

Spectrum

48MHz

24_48MHz

CPUCLK [1:0]

SDRAM [7:0]

SDRAM_F

IOAPIC

PCICLK [7:0]

8

2

8

2

2

3V66 [1:0]

X1

X2

XTAL

OSC

CPU

DIVDER

SDRAM

DIVDER

IOAPIC

DIVDER

PCI

DIVDER

3V66

DIVDER

SDATA

SCLK

IC

2

FS[3:0]

PD#

Control

Logic

Config.

Reg.

/ 2

REF1

{

PRODUCT PREVIEW documents contain information on new

products in the sampling or preproduction phase of development.

Characteristic data and other specifications are subject to change

without notice.