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ICS9250-11 Datasheet(PDF) 4 Page - Integrated Circuit Systems

Part # ICS9250-11
Description  Frequency Timing Generator for PENTIUM II/III Systems
PDF  8 Pages
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS9250-11 Datasheet(HTML) 4 Page - Integrated Circuit Systems

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ICS9250-11
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2VDD+0.3
V
Input Low Voltage
VIL
VSS-0.3
0.8
V
Input High Current
IIH
VIN = VDD
5
µA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
-5
IIL2
VIN = 0 V; Inputs with pull-up resistors
200
CL = Max loads; Select @ 100 MHz
160
CL = Max loads; Select @ 133 MHz
160
CL = Max loads; Select @ 100 MHz
75
CL = Max loads; Select @ 133 MHz
90
IDD3.3PD
CL = Max loads
200
IDD.25PD
Input address VDD or GND
100
Input Frequency
Fi
VDD = 3.3 V
14.318
MHz
Pin Inductance
1
Lpin
7nH
CIN
Logic Inputs
5
pF
COUT
Output pin capacitance
6
pF
CINX
X1 & X2 pins
13.5
18
22.5
pF
Transition time
1
Ttrans
To 1st crossing of target frequency
3
ms
Clk Stabilization
1
TSTAB
From VDD = 3.3 V to 1% target frequency
3
ms
tPZH,tPZL
Output enable delay (all outputs)
1
8
ns
tPHZ,tPLZ
Output disable delay (all outputs)
1
8
ns
TCPU-3V66
CPU @ 1.25V, 3V66 @ 1.5V
0
1.5
ns
T3V66-3V33
3V66 @ 1.5V, 3V33 @ 1.5V
1.5
3.5
ns
TCPU-IOAPIC CPU @ 1.25V, IOAPIC @ 1.25V
1.0
3.0
ns
1
Guaranteed by design, not 100% tested in production.
Input Low Current
µA
IDD3.3OP
Delay
1
mA
Input Capacitance
1
IDD.25OP
µA
Powerdown Current
Operating Supply
Current
mA
Skew
1



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