General Description

Features

ICS9250-12

Integrated

Circuit

Systems, Inc.

Block Diagram

Frequency Timing Generator for PENTIUM II/III Systems

9250-12 Rev B 2/23/00

Pin Configuration

56-pin SSOP

- 4CPUclocks(2.5V,100/133MHz)

- 8 PCI clocks, including 1 free-running (3.3V, 33MHz)

- 2CPU/2clocks(2.5V,50/66MHz)

- 3IOAPICclocks(2.5V,16.67MHz)

- 4 Fixed frequency 66MHz clocks(3.3V, 66MHz)

-2REFclocks(3.3V,14.318MHz)

- 1USBclock(3.3V,48MHz)

and PCI_STOP#.

IOAPIC, 3V66 and CPU/2 output clocks.

The ICS9250-12 is a main clock synthesizer chip for

Pentium II based systems using Rambus Interface DRAMs.

This chip provides all the clocks required for such a system

when used with a Direct Rambus Clock Generator (DRCG)

chip such as the ICS9212-01, 02, 03 and a PCI buffer 9112-17.

Spread Spectrum may be enabled by driving the SPREAD#

pin active. Spread spectrum typically reduces system EMI

by 8dB to 10dB. This simplifies EMI qualification without

resorting to board design iterations or costly shielding. The

ICS9250-12 employs a proprietary closed loop design,

which tightly controls the percentage of spreading over

process and temperature variations.

The CPU/2 clocks are inputs to the DRCG.

Key Specification:

•

CPU Output Jitter: 150ps

•

IOAPIC Output Jitter: 250ps

•

CPU/2, 3V66, PCI Output Jitter: 250ps

•

CPU (0:3) CPU/2 Output Skew: <175ps

•

PCI_F, PCI 1:7 Output Skew: <500ps

•

3V66 (0:3) Output Skew <250ps

•

IOAPIC (0:2) Output Skew <250ps

•

CPU to 3V66 (0:3) Output Offset: 0.0 - 1.5ns (CPU leads)

•

CPU to PCI Output Offset: 1.5 - 4.0ns (CPU leads)

•

CPU toAPIC Output Offset 1.5 - 4.0ns (CPU leads)

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any

information being relied upon by the customer is current and accurate.