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ICS9250-16 Datasheet(PDF) 6 Page - Integrated Circuit Systems

Part # ICS9250-16
Description  Frequency Generator & Integrated Buffers for Celeron & PII/III?
PDF  17 Pages
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS9250-16 Datasheet(HTML) 6 Page - Integrated Circuit Systems

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6
ICS9250-16
Byte 0: Control Register
(1 = enable, 0 = disable)
Byte 1: Control Register
(1 = enable, 0 = disable)
Byte 2: Control Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
These outputs are designed to be configured at power-on and are not
expected to be configured during the normal modes of operation.
2. PWD = Power on Default
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Notes:
1. Do not write in ID bits, these bits are for ICS internal use only.
2. Bit 0 will always read back 0. If readback/rewrite procedure is to
perform, user will need to ensure a "1" is written to Bit 0 for CPUCLK2
to maintain running status.
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