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ICS94203 Datasheet(PDF) 10 Page - Integrated Circuit Systems |
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ICS94203 Datasheet(HTML) 10 Page - Integrated Circuit Systems |
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10 / 18 page ![]() 10 ICS94203 Byte 21: ICS Reserved Register Notes: 1. PWD = Power on Default Byte 22: Output Rise/Fall Time Select Register Byte 20: Output Dividers Control Register Note: Changing bits in these registers results in frequency divider ratio changes. Incorrect configuration of group gear ratio can cause system malfunction. Notes: 1. PWD = Power on Default 2. The power on default for byte 16-20 depends on the harware (latch inputs FS[0:4]) or I 2C (Byte 0 bit [1:7]) setting. Be sure to read back and re-write the values of these 5 registers when VCO frequency change is desired for the first pass. 3. If Byte 8 bit 7 is driven to "1" meaning programming is intended, Byte 21-22 will lose their default power up value. Note: Each increment or decrement of bit 4 to 7 will introduce 100ps delay or advance on all of the above clocks. t i BD W Pn o i t p i r c s e D 7 t i BX 3 2 t i B l o r t n o C X U M r e d i v i D t u p t u O 6 t i BX 2 2 t i B l o r t n o C X U M r e d i v i D t u p t u O 5 t i BX 1 2 t i B l o r t n o C X U M r e d i v i D t u p t u O 4 t i BX 0 2 t i B l o r t n o C X U M r e d i v i D t u p t u O 3 t i BX 9 1 t i B l o r t n o C X U M r e d i v i D t u p t u O 2 t i BX 8 1 t i B l o r t n o C X U M r e d i v i D t u p t u O 1 t i BX 7 1 t i B l o r t n o C X U M r e d i v i D t u p t u O 0 t i BX 6 1 t i B l o r t n o C X U M r e d i v i D t u p t u O t i BD W Pn o i t p i r c s e D 7 t i B1 3 t i B w e k S I C P o t 6 6 V 3 6 t i B0 2 t i B w e k S I C P o t 6 6 V 3 5 t i B1 1 t i B w e k S I C P o t 6 6 V 3 4 t i B1 0 t i B w e k S I C P o t 6 6 V 3 3 t i B0 3 t i B w e k S C I P A O I o t 6 6 V 3 2 t i B1 2 t i B w e k S C I P A O I o t 6 6 V 3 1 t i B1 1 t i B w e k S C I P A O I o t 6 6 V 3 0 t i B0 0 t i B w e k S C I P A O I o t 6 6 V 3 t i BD W Pn o i t p i r c s e D 7 t i B0 k a e W = 1 , l a m r o N = 0 z H M 8 4 , 4 2 6 t i B0 k a e W = 1 , l a m r o N = 0 F E R / C I P A O I 5 t i B0 k a e W = 1 , l a m r o N = 0 I C P 4 t i B0 k a e W = 1 , l a m r o N = 0 F _ M A R D S 3 t i B0 k a e W = 1 , l a m r o N = 0 ] 1 1 : 0 [ M A R D S 2 t i B0 k a e W = 1 , l a m r o N = 0 6 6 V 3 1 t i B0 k a e W = 1 , l a m r o N = 0 1 U P C 0 t i B0 k a e W = 1 , l a m r o N = 0 0 U P C |
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