IDT54SLASH74FCT3244SLASHA datasheet(5/6 Pages) IDT

5 / 6 page

IDT54/74FCT3244/A

3.3V CMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

8.11

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable-

HIGH.

2. Pulse Generator for All Pulses: Rate

≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

3. If VCC is below 3V, input voltage swings should be adjusted not to exceed

VCC.

1.5V

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

tSU

tREM

tSU

HIGH-LOW-HIGH

PULSE

LOW-HIGH-LOW

PULSE

1.5V

SAME PHASE

INPUT TRANSITION

1.5V

VOH

tPLH

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

1.5V

tPLH

tPHL

VOL

CONTROL

INPUT

1.5V

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

SWITCH

GND

VOL

0.3V

tPLZ

tPZL

tPZH

tPHZ

1.5V

ENABLE

DISABLE

VOH

PRESET

CLEAR

CLOCK ENABLE

ETC.

Pulse

Generator

R T

D.U.T.

V CC

V IN

C L

V OUT

50pF

500

Ω

500

Ω

GND

Open

ENABLE AND DISABLE TIMES

PROPAGATION DELAY

SET-UP, HOLD AND RELEASE TIMES

PULSE WIDTH

SWITCH POSITION

TEST CIRCUITS AND WAVEFORMS

TEST CIRCUITS FOR ALL OUTPUTS

2779 drw 07

2779 drw 05

2779 drw 04

2779 drw 03

2779 drw 06

Test

Switch

Open Drain

Disable Low

Enable Low

Disable High

Enable High

GND

All Other tests

Open

DEFINITIONS:

CL=

Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse

Generator.

2779 lnk 08

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