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IDT7MP4045 Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT7MP4045 Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 8 page ![]() 2703 drw 01 PD0 31 29 9 11 13 15 17 19 21 23 25 1 3 5 7 27 33 63 61 41 43 45 47 49 51 53 55 57 35 37 39 59 PD1 – GND – GND 32 30 28 8 10 12 14 16 18 20 22 24 2 4 6 26 34 64 62 42 44 46 48 50 52 54 56 58 36 38 40 60 GND CS3 A16 I/O16 I/O17 I/O18 I/O19 A10 A11 A12 A13 I/O20 I/O21 I/O22 I/O23 GND I/O0 I/O1 I/O2 I/O3 VCC A7 A8 A9 I/O4 I/O5 I/O6 WE I/O7 CS1 PD0 A14 CS4 A17 OE I/O24 I/O25 I/O26 I/O27 A3 A4 A5 VCC A6 I/O28 I/O29 I/O30 I/O31 PD1 GND I/O8 I/O9 I/O10 I/O11 A0 A1 A2 I/O12 I/O13 I/O14 I/O15 GND CS2 A15 FEATURES: • High density 1 megabyte static RAM module (IDT7MP4145 upgradeable to 4 megabyte, IDT7MP4120) • Low profile 64 pin ZIP (Zig-zag In-line vertical Package) or 64 pin SIMM (Single In-line Memory Module) for IDT7MP4045 and 72 pin SIMM (Single In-line Memory Module) for IDT7MP4145 • Very fast access time: 15ns (max.) • Surface mounted plastic components on an epoxy laminate (FR-4) substrate • Single 5V ( ±10%) power supply • Multiple GND pins and decoupling capacitors for maxi- mum noise immunity • Inputs/outputs directly TTL-compatible PIN NAMES I/O0–31 Data Inputs/Outputs A0–17 Addresses CS1–4 Chip Selects WE Write Enable OE Output Enable PD0–1 Depth Identification VCC Power GND Ground NC No Connect 2703 tbl 01 Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE SEPTEMBER 1996 ©1996 Integrated Device Technology, Inc. DSC-2703/7 1 The IDT logo is a registered trademark of Integrated Device Technology Inc. NOTE: 1. Pins 2 and 3 (PD0 and PD1) are read by the user to determine the density of the module. If PD0 reads GND and PD1 reads GND, then the module has a 256K depth. DESCRIPTION: The IDT7MP4045/4145 is a 256K x 32 static RAM module constructed on an epoxy laminate (FR-4) substrate using 8 256K x 4 static RAMs in plastic SOJ packages. Availability of four chip select lines (one for each group of two RAMs) provides byte access. The IDT7MP4045 is available with access time as fast as 10ns with minimal power consumption. The IDT7MP4045 is packaged in a 64 pin FR-4 ZIP (Zig- zag In-line vertical Package)or a 64 pin SIMM (Single In-line Memory Module) where as the 7MP4145 is packaged in a 72 pin SIMM (Single In-line Memory Module). The 4045 ZIP configuration allows 64 pins to be placed on a package 3.65 inches long and 0.365 inches wide. The 7MP4045 ZIP is only 0.585 inches high, this low profile package is ideal for systems with minimum board spacing while the SIMM configuration allows use of edge mounted sockets to secure the module. All inputs and outputs of the IDT7MP4045/4145 are TTL- compatible and operate from a single 5V supply. Full asyn- chronous circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease of use. Identification pins are provided for applications in which different density versions of the module are used. In this way, the target system can read the respective levels of PD pins to determine a 256K depth. The contact pins are plated with 100 micro-inches of nickel covered by 30 micro-inches minimum of selective gold. PIN CONFIGURATION – 7MP4045(1) ZIP, SIMM TOP VIEW FUNCTIONAL BLOCK DIAGRAM OE WE 2703 drw 02 8 18 256K x 32 RAM 8 8 8 2 CS1 CS2 CS3 CS4 ADDRESS I/O0-31 PD IDT7MP4045 IDT7MP4145 256K x 32 CMOS STATIC RAM MODULE 15.2 |
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