| Electronic Components Datasheet Search |
|
83C51KB Datasheet(PDF) 14 Page - Intel Corporation |
|
|
|||||||||||||||||||||||||||||
83C51KB Datasheet(HTML) 14 Page - Intel Corporation |
|
14 / 19 page ![]() 14 83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER VOH1 Output High Voltage (P3.0, P3.2, P3.3 without 1.8K Ohm pullup) VCC-0.3 VCC-0.7 VCC-1.5 VIOH= -8 µA IOH= -25 µA IOH= -50 µA VOH2 Output High Voltage (P3.0, P3.2, P3.3 with 1.8K Ohm pul- lup) VCC-0.3 VCC-0.7 VCC-1.5 VIOH= -0.15 mA IOH= -0.50 mA IOH= -1.0 mA RRST Reset Pulldown Resistor 40 225 K Ohm RCD Pull Up Resistance (P3.0, P3.2, P3.3 with 1.8K Ohm pul- lup) 1.2 1.8 2.9 K Ohm CIO Pin Capacitance 10 pF @1MHz, 25°C IIL Logical 0 Input Current (Port 0, 1, 2, 3, except P3.0, P3.2, P3.3) -50 µA VIN=0.45V IIL1 Logical 0 Input Current (P3.0, P3.2, P3.3 without 1.8K Ohm pullup) -250 µA VIN=0.45V IIL2 Logical 0 Input Current (P3.0, P3.2, P3.2 with 1.8K Ohm pul- lup) -1.5 -4.5 mA VIN=0.45V ITL Logical 1-to-0 Transiton Cur- rent (Port 0, 1, 2, 3) -650 µA VIN=2.0V ITL1 Logical 1-to-0 Transition Cur- rent (P3.0, P3.2 or P3.3 with 1.8K Ohm pullups) -4.5 mA VIN = 2.0V Table 7. D.C. Characteristics (Continued) Symbol Parameter Min Typical (note 1) Max Unit Test Condition NOTE: 1. Typical values are obtained using VCC=5.0V, TA=25°C and are not guaranteed. 2. Under steady state (non-transient) conditions, IOL must be externally limited as follow: Maximum IOL per Port Pin—Port 0, 1, 2, P3.1-P3.3: 10mA Maximum IOL per Port Pin—P3.4-P3.7: 22mA Maximum IOL per 8-bit port—Port 0-2: 15mA Ports 3: 95mA Maximum Total IOL for AllOutput Pins: 110mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 3. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4V to be superimposed on the low level outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance dis- charging into the Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitive loading exceeds 100pF, the noise pulses on these signals may exceed 0.8V. It may be desirable to qualify signals with a Schmitt Trigger, or CMOS-level input logic. 4. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 VCC specification when the address lines are stabilizing. |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |