80C196MH datasheet(13/41 Pages) INTEL

13 / 41 page

8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER

BHE#

Byte High Enable. During 16-bit bus cycles, this active-low

output signal is asserted for word reads and writes and for

high-byte reads and writes to external memory. BHE#

indicates that valid data is being transferred over the upper

half of the system address/data bus.

BHE#, in conjunction with A0, selects the memory byte to be

accessed:

BHE#

Byte(s) Accessed

both bytes

high byte only

low byte only

P5.5/WRH#

BUSWIDTH

Bus Width. When enabled in the chip configuration register,

this active-high input signal dynamically selects the bus width

of the bus cycle in progress. When BUSWIDTH is high, a 16-

bit bus cycle occurs; when BUSWIDTH is low, an 8-bit bus

cycle occurs. BUSWIDTH is active during a CCR fetch.

P5.7

COMP3

COMP2

COMP1

COMP0

Event Processor Array (EPA) Compare Pins. These

signals are the output of the EPA compare modules. These

pins are multiplexed with other signals and may be

configured as standard I/O.

P2.3

P2.6/CPVER

P2.5/PACT#

P2.4/AINC#

CPVER

Cumulative Program Verification. This active-high output

signal indicates whether any verify errors have occurred

since the device entered programming mode. CPVER

remains high until a verify error occurs, at which time it is

driven low. Once an error occurs, CPVER remains low until

the device exits programming mode. When high, CPVER

indicates that all locations have programmed correctly since

the device entered programming mode.

P2.6/COMP2

EA#

External Access. This active-low input signal directs

memory accesses to on-chip or off-chip memory. If EA# is

low, the memory access is off-chip. If EA# is high and the

memory address is within 2000H–2FFFH, the access is to

on-chip ROM or OTPROM. Otherwise, an access with EA#

high is to off-chip memory.

EA# is sampled only on the rising edge of RESET#.

If EA# = V

EA on the rising edge of RESET#, the device enters

the programming mode selected by PMODE.3:0.

For devices without ROM, EA# must be tied low.

—

EPA1

EPA0

I/O

Event Processor Array (EPA) Input/Output pins. These

are the high-speed input/output pins for the EPA

capture/compare modules. These pins are multiplexed with

other signals and may be configured as standard I/O.

P2.2/PROG#

P2.0/PVER

Table 7. Signal Descriptions (Continued)

Signal

Name

Type

Description

Multiplexed

With

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