M80C86M80C86-2

Table 1 Pin Description

(Continued)

Symbol

Pin No

Type

Name and Function

RD

32

O

READ

Read strobe indicates that the processor is performing a

This signal is used to read devices which reside on the M80C86

has floated

This floats to 3-state OFF in ‘‘hold acknowledge’’

READY

22

I

READY

is the acknowledgement from the addressed memory or

IO device that it will complete the data transfer The READY signal

from memoryIO is synchronized by the M82C84A Clock Generator

to form READY This signal is active HIGH The M80C86 READY

input is not synchronized Correct operation is not guaranteed if the

setup and hold times are not met

INTR

18

I

INTERRUPT REQUEST

is a level triggered input which is sampled

during the last clock cycle of each instruction to determine if the

processor should enter into an interrupt acknowledge operation A

subroutine is vectored to via an interrupt vector lookup table

located in system memory It can be internally masked by software

resetting the interrupt enable bit INTR is internally synchronized

This signal is active HIGH

TEST

23

I

TEST

input is examined by the ‘‘Wait’’ instruction If the TEST input

is LOW execution continues otherwise the processor waits in an

‘‘Idle’’ state This input is synchronized internally during each clock

cycle on the leading edge of CLK

NMI

17

I

NON-MASKABLE INTERRUPT

an edge triggered input which

causes a type 2 interrupt A subroutine is vectored to via an

interrupt vector lookup table located in system memory NMI is not

maskable internally by software A transition from a LOW to HIGH

initiates the interrupt at the end of the current instruction This input

is internally synchronized

RESET

21

I

RESET

causes the processor to immediately terminate its present

activity The signal must be active HIGH for at least four clock

cycles It restarts execution as described in the Instruction Set

description when RESET returns LOW RESET is internally

synchronized

CLK

19

I

CLOCK

provides the basic timing for the processor and bus

controller It is asymmetric with a 33% duty cycle to provide

optimized internal timing

40

GND

1 20

GROUND

Both must be connected

MNMX

33

I

MINIMUMMAXIMUM

indicates what mode the processor is to

operate in The two modes are discussed in the following sections

3