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CD40147BMS Datasheet(PDF) 6 Page - Intersil Corporation |
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CD40147BMS Datasheet(HTML) 6 Page - Intersil Corporation |
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6 / 8 page ![]() 7-76 CD40147BMS Logic Diagram FIGURE 1. TRUTH TABLE (Negative Logic) INPUTS OUTPUTS 0123456789 D C B A 0 1 X X X X X X X X X 0 0 1 X X X X X X X X 0 0 0 1 X X X X X X X 0 0 0 0 1 X X X X X X 0 0 0 0 0 1 X X X X X 0 0 0 0 0 0 1 X X X X 0 0 0 0 0 0 0 1 X X X 0 0 0 0 0 0 0 0 1 X X 0 0 0 0 0 0 0 0 0 1 X 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 = High level 1 = Low level X = Don’t care 8 8 5 8 * 7 7 4 7 * 6 6 3 6 * 5 5 2 5 * 4 4 1 4 * 9 10 9 * 3 13 3 * 2 2 12 2 * 1 11 1 * 0 15 0 * 8 9 6 7 4 5 2 3 1 FUNCTIONAL GATING 6 7 4 5 2 3 8 9 4 5 6 8 9 1 0 3 2 5 4 7 6 9 8 14 D 6 C 7 B 9 A VDD VSS 7 * ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK |
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