7-357

CD4018BMS

Timing Diagram

FIGURE 11. TIMING DIAGRAM

FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A

FUNCTION OF LOAD CAPACITANCE (RESET TO

Q)

FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A

FUNCTION OF CLOCK INPUT FREQUENCY

300

200

100

0

20

40

60

80

100

LOAD CAPACITANCE (CL) (pF)

15V

10V

SUPPLY VOLTAGE (VDD) = 5V

10

2

6

8

2

4

6

8

2

4

6

8

4

2

4

24

8

INPUT FREQUENCY (fCL) (HZ)

1

62

4

8

62

4

8

62

4

8

62

4

8

6

SUPPLY VOLTAGE

(VDD) = 15V

10V

10V

5V

CL = 50pF

CL = 15pF

DON’T CARE UNTIL PRESET “GOES HIGH”

(“DATA” INPUT TIED TO Q5 FOR DECADE COUNTER CONFIGURATION)

CLOCK

RESET

PRESET

JAM 1

JAM 2

JAM 3

JAM 4

JAM 5

Q1

Q2

Q3

Q4

Q5