7-1089

CD4094BMS

FIGURE 1. LOGIC DIAGRAM

TRUTH TABLE

CL

∆

OUTPUT

ENABLE

STROBE

DATA

PARALLEL OUTPUTS

SERIAL OUTPUTS

Q1

QN

QS*

Q’S

0X

X

OC

OC

Q7

NC

0X

X

OC

OC

NC

Q7

1

0

X

NC

NCQ7NC

1100

QN-1

Q7

NC

1111

QN-1

Q7

NC

1

1

1

NC

NC

NC

Q7

∆ = Level Change

Logic 1 = High

X = Don’t Care

Logic 0 = Low

NC = No Change

OC = Open Circuit

* At the positive clock edge information in the 7th shift register stage is transferred to the 8th register stage

and the QS output

DQ

Q

8

CL

CL

TR

TR

LATCH

8

3 -

STATE

8

TR

TR

LATCH

2

3 -

STATE

2

DQ

1

CL

CL

TR

TR

TR

TR

p

n

pn

TR

TR

CL

CL

5

2

3

1

15

DQ

2

CL

CL

CL

CL

p

n

CL

CL

p

n

11

STAGES

3 - 7

6

7

14 13 12

4

SERIAL

OUT

Q’S

10

SERIAL

OUT

QS

9

VDD

VSS

PROTECTED BY

CMOS PROTECTION

NETWORK

*

*

*

*

SERIAL

IN

CLOCK

STROBE

OUTPUT

ENABLE

LATCH

1

3-STATE

1

VDD

VSS

pn

Q1

Q2

Q3 Q4 Q5 Q6 Q7

Q8

*