7-1180

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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CD4512BMS

CMOS Dual 4-Bit Latch

Pinout

CD4512BMS

TOP VIEW

Functional Diagram

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

D0

D1

D2

D3

D4

D5

VSS

D6

VDD

SEL. OUTPUT

C

B

A

INHIBIT

D7

3-STATE DISABLE

3-STATE DISABLE

INHIBIT

D0-1

D1-2

D2-3

D3-4

D4-5

D5-6

D6-7

D7-9

A-11

B-12

C-13

10

15

14 SELECT

OUTPUT

VDD = 16

VSS = 8

CD4512BMS

CHANNELS

INPUTS

SELECT

CONTROL

Features

• High-Voltage Types (20-Volt Rating)

• 3-State Outputs

• Standardized, Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

• 5V, 10V, and 15V Parametric Ratings

• Maximum Input Current of 1

µA at 18V Over Full Pack-

• Noise Margin (Full Package-Temperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets all Requirements of JEDEC Tentative Standard

No. 13B, "Standard Specifications for Description of

‘B’ Series CMOS Devices"

Applications

• Digital Multiplexing

• Number-sequence Generation

• Signal Gating

Description

CD4512BMS is an 8-channel data selector featuring a three-

state output that can interface directly with, and drive, data

lines of bus-oriented systems.

The CD4512BMS is supplied in these 16 lead outline

packages:

Braze Seal DIP

H4S

Frit Seal DIP

H1E

Ceramic Flatpack

H3X

December 1992

File Number

3340