CDP1871ACE datasheet(8/10 Pages) INTERSIL

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4-73

and read by the CPU, at which time the next key pressed in

the scanning order is detected. If the ﬁrst key remains closed

after the CPU reads the data and resets the DA output, on

the low-to-high transition of TPB, an auxiliary signal (RPT) is

generated and is available to the CPU to indicate an auto-

repeat condition. The RPT output is reset high at the end of

the debounce delay after the depressed key is released.

The DEBOUNCE input provides a terminal connection for an

external user-selected RC circuit to eliminate false detection

of a keydown condition caused by keyboard noise. The oper-

ation of the DEBOUNCE circuit is shown in Figure 2 (Pin

36). When a valid keydown is detected, the on-chip active-

resistor device (RN) is enabled and the external capacitor

(CX) is discharged, providing a key closure debounce time ≅

RNCX. This discharge is sensed by the Schmitt-trigger

inverter, which clocks the DA ﬂip-ﬂop (latching the DA output

low and inhibiting the scan clock). (The DA F/F is reset by

the low-to-high transition of TPB when the CS inputs are

enabled). When a valid key-release is detected RN is dis-

abled and CX begins to charge through the external resistor

(RX), providing a key-release debounce time ≅ RXCX. This

charge time is again sensed by the Schmitt-trigger inverter,

enabling the scan clock to continue on the next high-to-low

transitions of TPB, after the current keycode data is read by

the CPU.

Dynamic Electrical Speciﬁcations At TA = -40 to +85oC, VDD ±5%, Unless Otherwise Speciﬁed

PARAMETER

VDD

(V)

LIMITS

UNITS

CDP1871AD, CDP1871AE

CDP1871ACD, CDP1871ACE

MIN

(NOTE 1)

TYP

MAX

MIN

(NOTE 1)

TYP

MAX

Clock Cycle Time

tCC

Note 2

Clock Pulse Width High

tCWH

100

Data Available Valid Delay

tDAL

260

500

260

500

130

250

Data Available Invalid Delay

tDAH

150

Scan Count Delay

(Non-Repeat)

tCD1

850

1900

850

1900

425

950

Data Out Valid Delay

tCDV

120

250

120

250

125

Data Out Hold Time

tCDH

100

200

100

200

100

Repeat Valid Delay

tRPL

150

400

150

400

200

Repeat Invalid Delay

tRPH

350

700

350

700

170

350

NOTES:

1. Typical values are for TA = +25

oC and nominal V

DD.

2. tCC = tCWH + tCWL

tCWL = tCD1 + KC

k = 0.9ns per pF

c = Keyboard capacitance (pF)

CDP1871A, CDP1871AC

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