ADCMP604/ADCMP605

Data Sheet

The hysteresis control pin appears as a 1.25 V bias voltage seen

through a series resistance of 70 kΩ ± 20% throughout the

hysteresis control range. The advantages of applying hysteresis

in this manner are improved accuracy, improved stability, reduced

component count, and maximum versatility. An external bypass

capacitor is not recommended on the HYS pin because it would

likely degrade the jitter performance of the device and impair the

latch function. As described in the Using/Disabling the Latch

Feature section, hysteresis control need not compromise the

latch function.

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HYSTERESIS RESISTOR (kΩ)

CROSSOVER BIAS POINTS

Rail-to-rail inputs of this type, in both op amps and comparators,

have a dual front-end design. Certain devices are active near the

predetermined point in the common-mode range, a crossover

current reverses and there are changes in measured offset

voltages and currents.

MINIMUM INPUT SLEW RATE REQUIREMENT

With the rated load capacitance and normal good PCB design

practice, as discussed in the Optimizing Performance section,

these comparators should be stable at any input slew rate with

no hysteresis. Broadband noise from the input stage is observed

in place of the violent chattering seen with most other high

speed comparators. With additional capacitive loading or poor

bypassing, oscillation is observed. This oscillation is due to the

high gain bandwidth of the comparator in combination with

feedback parasitics in the package and PCB. In many applications,

chattering is not harmful.

Rev. B | Page 12 of 14