7

HIP0063

tion. If there is still a problem in verifying the data sent, a

communication error and further diagnosis is required. If the 16-

bit mode is used, the data sent in the first byte should be the

same as the data received in the second byte.

Pin Descriptions

+5V logic level voltage. The normal operating voltage range is

Threshold, the POR forces a reset which turns-off the Gate

Drive outputs.

All MOSFETs are normally controlled by the HIP0063 and are

separately biased by a Battery or System level power supply.

forces over-voltage shutdown under excessive high voltage

tions to switch off the Gate Drive output.

GND Pin

The GND (Ground) pin is the 5V logic supply ground for the IC

and is a common ground for all functions on the chip.

SCK SPI Clock Pin

SCK is the bit shift clock input of the SPI interface and is con-

nected to the SCK pin of the master device. Available control bits

are clocked into the SI serial data input on the rising edge of the

SCK pulse. SCK is low when CS goes active low. Each rising

edge transition shifts in 1 bit of data. The SCK clock pulse has a

50% duty cycle and a CMOS logic level. The negative edge tran-

sition of SCK shifts available data out of the SO data output pin.

SI Serial Data In Pin

SI is the Serial Data Input pin of the SPI interface and receives

command data from the master device on the rising edge of SCK

when CS is low. Six Gate Drive control bits and the HLOS moni-

tor bit are contained in the serial data byte at the SI input. The SI

data input is an 8-bit or 16-bit control byte sent MSB first. (Refer

to Table 1 for bit information.) Outputs are switched on with “1”

state. Unused bits, including the HLOS bit, are set to the “0”

state. This is a CMOS logic level input with an internal active pull-

down.

SO Serial Data Out Pin

SO is the Serial Data Output pin of the SPI interface and trans-

mits control status and fault data to the master device. The SO

Serial Data Output is switched to an active state while CS is low

and three-states when CS is high or HLOS is active. Otherwise,

this is a CMOS logic level output with available data shifted out at

SO on the negative edge of the SCK clock pulse. The normal SO

output data is the same as the SI input data and is returned MSB

first. If any of the channels are returning fault bits, the respective

bit will be returned as a complement. If the HLOS control mode is

active, the HLOS bit is returned as a complement. (Refer to Table

1 for bit information. Refer to the Input Control section of Applica-

tions for further details on transfer of control with HLOS/PWM

switching).

CS Chip Select (Enable) Pin for the SPI interface

The CS Chip Select is an active low input pin. SPI bus commu-

nication with the master device becomes active when CS is

switched low. When CS is active low, data may then be shifted

into SI and out of SO with each SCK clock pulse. When CS

goes high, the SO output switches to three-state and SPI com-

munication is terminated. When CS goes active low, fault bits in

the internal fault register are latched (with no further change

during data transmission). When CS goes high, the fault status

register is then open to new fault information. The CS input is a

CMOS logic level output with an internal active pullup.

PI0 Thru PI5 Parallel Inputs

Each gate control channel has an OR’d input for control of the

Gate Drive output. The control bits from the SPI input are OR’d

with the respective parallel input control bit. Turn-on control for

each channel may be initiated either from the SPI control input

or the independent parallel input. Each PIx input has CMOS

logic level control with an internal active pulldown and must be

switched high to turn-on the Gate Drive output. (Refer to the

Input Control section of Applications for further details on trans-

fer of control with HLOS/PWM switching).

HLOS, HPW01, HPW45 Pins

The HLOS pin is switched high by an I/O select line to initiate

PWM operation using the HPW01 and HPW45 pins. When

active, the SPI inputs and the PI0, PI1, PI4 the PI5 parallel

inputs are disabled. The channels 0 and 1 are under the direct

control of the HPW01 pin and channels 4 and 5 are under the

direct control of the HPW45 pin. Channels 2 and 3 have direct

and independent control by the PI2 and PI3 inputs. These pins

have CMOS logic level control. The HLOS pin has an internal

active pullup and the HPW01 and HPW45 have internal active

pulldowns. The state of the HPW01 and HPW45 pins are “don’t

care” when the HLOS pin is low.

Go Thru G5 Gate Drive Pins

The Gate Drive pins each drive external NDMOS or equivalent

MOSFETs to provide low side switching control of the output

loads. The Gate Drive pins are switched high to turn-on the

MOSFET output. The Gate Drive output is switched to a low

duty cycle mode during over-current fault conditions or switched

D0 Thru D5 Drain Monitor Pins

The Drain Monitor input pins sense an over-current fault at the

drain of the output MOSFET driver by detecting the drain volt-

age to be higher than an internal voltage reference when the

output is on. Open Load conditions are sensed at the Drain

Monitor input when the output is off by detecting the drain volt-

age of the MOSFET to less than in internal reference. For each

channel, a single fault bit is returned for either condition. For

each channel, an internal zener diode connects the Drain Mon-

itor input to the Gate Drive output to provide voltage clamping

when an inductive load is switched off. When the drain to gate

zener diode conducts, the gate is turned-on sufficiently to

clamp the inductive kick voltage pulse.