HIP7010 datasheet(10/20 Pages) INTERSIL

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block. The STATE block controls the ﬂow of all data between

the SERIAL and SENDEC blocks. The STATE block also con-

trols Host/HIP7010 handshaking, automatic J1850 bus arbi-

tration, break recognition, CRC checking, and many other

features. In addition to the three major blocks the HIP7010

includes CRC generator/checker hardware, a Status/Control

Timing Generator

The timing generator, as its name suggests, generates all

internal timing pulses required for the SERIAL, SENDEC,

STATE, and CRC circuits. The CLK input pin is appropriately

divided to produce an internal 2MHz clock which results in a

1MHz SERIAL transfer rate and VPW J1850 symbol timing

with 1

µs accuracy. The CLK pin of the HIP7010 can be driven

with a variety of common microcontroller frequencies. Fre-

quency selection is accomplished via three bits in the Sta-

tus/Control register. See Status/Control Register for more

details.

The Serial Interface (SERIAL) System

Overview

The SERIAL system handles all interface between the Host

microcontroller and the HIP7010. The SERIAL system is

designed to interface directly with the Serial Peripheral Inter-

face (SPI) systems of the Intersil CDP68HC05 family of micro-

controllers. Identical interfaces are found on the 68HC11 and

HC16 families. Compatible systems are found on most popu-

lar microcontrollers.

Serial data words are simultaneously transmitted and

received over the SOUT/SIN lines, synchronized to the SCK

clock stream. The word size is ﬁxed at 8-bits. A series of

eight clocks is required to transfer one word. With the excep-

tion of Status/Control Register transfers (described later), all

SERIAL transfers use a single eight bit shift register within

the HIP7010. The serial bits are “shifted out” on the SOUT

pin, most signiﬁcant bit (MSB) ﬁrst, from the shift register. As

each bit shifts out one end of the shift register, the data on

the SIN input pin is, usually, shifted into the other end of the

same shift register. After eight clocks, the original contents of

the shift register have been entirely transmitted on the SOUT

pin and replaced by the byte received on the SIN pin.

Most Host micros which include a synchronous serial inter-

face, operate their interface in a manner compatible with the

HIP7010s implementation. The result of each 8-bit SERIAL

transfer is that the contents of the HIP7010s shift register

and the Host’s shift register have effectively been “swapped”.

SERIAL Bus Timing

The SCK output of the HIP7010 is used to synchronize the

movement of data both into and out of the device on its SIN

and SOUT lines. As stated above, the Host and the HIP7010

are capable of exchanging a byte of information during a

sequence of eight clocks generated on the SCK pin. The

relationship between the clock signal on SCK and the data

on SIN and SOUT is shown in Figure 7.

At least tLEAD prior to each series of eight clocks, the SAC-

TIVE output of the HIP7010 is driven low. SACTIVE remains

low until a minimum of tLAG after the last clock transition.

When interfacing to a CDP68HC05 SPI compatible Host, the

SACTIVE output would normally be connected to the SS input

of the Host. The trailing edge of the SACTIVE signal can also

be used as a ﬂag to Hosts which don’t automatically recognize

the transfer of a serial byte.

The quiescent state of SCK is low. Once a transfer is initi-

ated, the rising edge of each SCK pulse places the next bit

on the SOUT line and the falling edge is used to latch the bit

input on SIN.

The Host must adhere to this same timing, by meeting the input

setup time requirements of SIN valid before the trailing edge of

SCK (see Electrical Speciﬁcation for details) and latching

the SOUT data on the same edge. When interfacing the

HIP7010 to a CDP68HC05 SPI compatible Host, the SPI inter-

face should be programmed with CPHA = 1 and CPOL = 0.

At all times, other than during an actual SERIAL transfer

between the HIP7010 and its Host, the SCK and SOUT pins

are held in a high impedance state. This allows other devices

connected to the Host via the SERIAL bus to be accessed

when the HIP7010 is not transferring data. Utilization of the

SERIAL bus by the HIP7010 is less than 5%, leaving signiﬁ-

cant bandwidth for other transfers. When held in the high

impedance state, a pair of integrated pull-down devices on the

SCK and SOUT pull the pins to ground, if they are not driven

by another source. See Applications Information for a

detailed discussion of SERIAL bus utilization.

SCK

SOUT

SIN

SACTIVE

SCK NORMALLY LOW

MSB

LSB

INTERNAL STROBE FOR LATCHING DATA IN HIP7010

MSB

LSB

FIGURE 7. SERIAL BUS TIMING

HIP7010

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