HIP7020AP datasheet(3/11 Pages) INTERSIL

3 / 11 page

Absolute Maximum Ratings

Thermal Information

Supply Voltage, VBATT . . . . . . . . . . . . . . . . . . . . . . . . . -20V to +24V

Short Term Supply Voltage, VBATT, 1s Max. (Note 2) . . . . . . . +35V

J1850 Bus Input Voltage, VBUS IN . . . . . . . . . . . . . . . . . . . . . . ±20V

J1850 Bus Load Current, IBO. . . . . . . . . . . . . . . . . . . . .Self-Limiting

TX Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to 7V

RX Logic Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA

Load Dump (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V

BUS Transient Susceptibility . . . . . . . . . . . . . . . . . . . . . . . (Note 3)

ESD:

BUS OUT, BATTERY Pins, (Air Gap, Note 4) . . . . . .

±9kV

BUS OUT, BATTERY Pins, (Direct, Note 4) . . . . .

±4.5kV

All Other Pins (Direct, Note 4) . . . . . . . . . . . . . . . . . .

±2kV

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 125oC

Thermal Resistance (Typical, Note 1)

JA (

oC/W)

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

120

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

160

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-40oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTES:

θJA is measured with the component mounted on an evaluation PC board in free air.

2. Fault capability of the J1850 Bus Transceiver includes reverse battery, load dump and latch-up tolerance to

±200mA on any terminal. The

Short Term Power Supply Voltage capability is 35V for a maximum of 1s. Continued operation at this voltage may cause thermal shutdown.

3. Transient Susceptibility Bus and Battery Pins Per SAE J1113, Aug 1987, Figures 7 Test Pulses 1, 2, 3A and 3B at -50V, +100V and

±200V

respectively.

4. ESD Conditions - SAE J1113; Aug 1987.

BUS OUT & BATTERY Pins: Air Gap and Direct Contact Discharge; R = 2k

Ω, C = 150pF

All Other Pins: Direct Contact Discharge; R = 1.5k

Ω, C = 100pF

Electrical Speciﬁcations

9.0V

≤ V

BATT ≤ 16V; RS = 56.2kΩ±1%; except as noted, RBS = 500Ω to 1500Ω and τ =RBSCBS =5µs.

All voltages are measured with respect to ground and the TA Range of -40

oC to 125oC shall not be

exceeded during test unless otherwise speciﬁed. For test detail, refer to the Block Diagram, Figures 3

and 4 Test Circuits and Figures 5 and 6 Waveforms.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Idle Supply Current

IBATT

BUS OUT Open; No Bus Signal;

VBATT = 12.6V; VTX Low

200

350

µA

Operating Voltage Range

VBATT

(Note 5)

Supply Current,

BUS OUT Short to GND

IBATT(SG)

BUS OUT Short to GND, VTX High

Supply Current,

BUS OUT Short to BATT

IBATT(SB)

BUS OUT to VBATT; IBO = 0 mA

VTX High

VTX Low

350

µA

Thermal Shutdown Temperature

TSD

(Note 6)

150

170

Thermal Shutdown Hysteresis

TSDHYS

(Note 6)

TX CMOS/TTL INPUT WITH/PULL DOWN

Input Bias Current, TX

ITX

VTX = 7V; (Note 7)

µA

Input Low Voltage

VIL

0.8

Input High Voltage

VIH

2.0

Input Capacitance

CTX

2-5

BUS OUT

BUS OUT High Voltage

VBOH

VTX High

6.6

8.5

BUS OUT Low Voltage

VBOL

Bus Load, RBS = 1.5kΩ; VTX Low

0.1

BUS OUT Voltage, Low Battery

VBOH(PSL) 6V ≤ VBATT < 9V; VTX High

Note

8.5

Source Current, Bus Low

IBO_LIMIT

-20V

≤ VBUS OUT < [VBOH (Measured) - 0.8V];

VTX High

-20

-42

BUS OUT During LOOPBACK

VLOOPBACK LB EN Low, VTX High

HIP7020

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