ISL6505AEVAL2 datasheet(12/17 Pages) INTERSIL

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signals it is driving. Since the pin can nominally sink 1.2mA

with only a 0.1V drop, a 1k

Ω resistor will match that

condition. The minimum input low logic level is typically

around 25-30% of the 1.2V supply (0.3V in this example),

and the 0.1V is well below it. So a resistor pull-up value as

low as 1k

Ω is acceptable to get faster rise times.

Linear Regulator (VOUT1) Compensation

VOUT1 is a linear regulator, with an on-chip amplifier, and

external FET and feedback resistors. The output capacitors

should be selected to allow the output voltage to meet any

dynamic regulation requirements, paying attention to their

parasitic components ESR (Effective Series Resistance) and

ESL (Effective Series inductance).

VOUT1 is internally compensated to cover a wide range of

load currents; however the output filter capacitor must be

chosen carefully. Ideally, the capacitor value and its ESR

combine to create a zero that cancels one of the amplifier

poles. However, this is only a first order approximation, since

that pole moves with load current, for example. In addition,

there are high frequency poles that may come into play

under certain conditions.

A lower capacitor ESR improves transient response. When

the output load changes quickly (faster than the amplifier

itself can respond), the differential load current is sourced or

sinked by the capacitor, until the regulator can respond and

catch up. In this case, the higher the ESR, the larger the

voltage drop across it, and thus the larger the voltage

transient on the output is.

However, lower output capacitor ESR pushes the zero

frequency higher, reducing the regulator phase margin.

Thus, it may be difficult to simultaneously satisfy both tight

dynamic regulation and a good stable loop with high phase

margin.

There are many factors that affect VOUT1 stability, such that

a simple equation or formula is not practical. So the

recommendation is to choose a value from Figure 11, which

shows capacitance versus ESR. Values inside the polygon

will result in stable conditions over a full load range of 10mA

to 3A. Choosing a value outside the polygon is NOT

recommended; it may work in some cases, but the margin

may be much smaller. In addition, there are manufacturing

tolerances (of both the IC and the capacitor), load variations,

temperature, FET selection, and many other factors that can

create the potential for problems.

Other Considerations

See COMPONENT SELECTION section for more details on

choosing Q6. The minimum load assumed is 10mA. The

maximum load is based primarily on the ability of the FET to

dissipate the heat; for stability, the assumption was 3A.

The FET selection can affect the compensation. With light

(or no) load, the gm of the FET is very low, and looks like a

high series resistance to the load, thus reducing the loop

gain, and moving the pole formed by the output capacitor

down by as much as several decades. In addition, the FET

input capacitance can vary from hundreds to thousands of

pF; (higher gm FETs such as logic level FETs typically have

a higher gate capacitance). The FET capacitance, along with

the amplifier driver resistance is included in the stability

calculations. Finally, the slewing of the FET gate

(determined by its capacitance) affects the transient

response. So a lot of the parameters are inter-related.

Note that the latest low-ESR ceramic capacitors are NOT

well suited for this application; the ESR (typically only a few

Ω) is too low to be inside the polygon, for any typical value

of capacitance.

1V2VID Regulator (VOUT2) Compensation

1V2VID is an on-chip linear regulator, which is internally

compensated to cover loads up to its maximum rating of

180mA. However, the output capacitor choice can affect the

stability. The recommendation is to use a tantalum (or

similar) capacitor around 10µF (with high ESR in the 1-5m

Ω

range), in parallel with a ceramic 1µF capacitor (with low

ESR in the 10m

Ω range). The two capacitors (dominated by

the tantalum) will create a zero that will help cancel the pole

of the internal regulator; the ceramic capacitor will help the

frequency response. Note that a single bigger ceramic

capacitor is NOT recommended; the higher ESR is

necessary.

FIGURE 11. VOUT1 OUTPUT CAPACITOR SELECTION

100

1000

10000

CAPACITANCE (µF)

1000

100

ISL6505

ISL6505AEVAL2 Datasheet(PDF) 12 Page - Intersil Corporation

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