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UPC8101 Datasheet(PDF) 1 Page - NEC |
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UPC8101 Datasheet(HTML) 1 Page - NEC |
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1 / 3 page ![]() FEATURES INTERNAL BLOCK DIAGRAM PRELIMINARY DATA SHEET 3 V, SILICON MMIC 150 MHz QUADRATURE MODULATOR UPC8101GR ELECTRICAL CHARACTERISTICS (TA = 25°C, LO PIN = -10 dBm, VENABLE ⊕1.8 V, ZL = 50 Ω) • OPERATING FREQUENCY: 50 to 150 MHz • I/Q INPUT FREQUENCY RANGE: DC to 500 kHz • DIGITAL 90 ° PHASE SHIFTER • ALLOWABLE BIAS VOLTAGE: 2.7 to 5.5 V • POWER SAVE: "SLEEP" MODE • SMALL SIZE SSOP20 SURFACE MOUNT PACKAGE • TAPE AND REEL PACKAGING OPTION AVAILABLE DESCRIPTION The UPC8101GR is a Silicon Monolithic Integrated Circuit (MMIC) which is manufactured using NEC's 20 GHz fT NESAT III process. The Quadrature Modulator was designed for digital mobile communications in general, and the CT2 band requirements in particular. Operating on DC bias voltages as low as 2.7 volts, this IC is ideal for handheld/portable designs. The UPC8101GR takes an external LO signal, and digitally divides its frequency by two to generate the quadrature LO required for the dual internal mixer circuits. These mixers also receive external in-phase (I) and quadrature (Q) signals. The up-converted outputs of the mixers are combined in a differ- ential output amplifier. The resultant output signal is at fre- quency of fLO/2 + fI/Q. Buffers are provided at the LO, I and Q inputs, and filtering is provided between the digital frequency divider and the mixers. The device can be powered down by grounding the Enable pin. NEC's stringent quality assurance and test procedures en- sure the highest reliability and performance. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 F/F 270˚ 180˚ 90˚ 0˚ LPF LPF REG. 1. LOCAL IN 2. LOCAL IN 3. GND 4. Q-BIAS 5. Q-BIAS 6. GND 7. Q-INPUT 8. Q-INPUT 9. GND 10. IF OUTPUT 11. VCC 12. VENABLE 13. I-INPUT 14. I-INPUT 15. GND 16. I-BIAS 17. I-BIAS 18. GND 19. N.C. 20. GND Note: 1. fLO = 300.1 MHz, fI/Q = 36 kHz at VCC/2 + 1 Vp-p. Note: N.C. = No Connection PART NUMBER UPC8101GR PACKAGE OUTLINE S20 (SSOP 20) VCC = 2.7 V VCC = 5.5 V SYMBOLS PARAMETERS AND CONDITIONS UNITS MIN TYP MAX MIN TYP MAX ICC Circuit Current mA 10 15 22 17 24.5 32 VENABLE ≤ 1.0 V mA 0.33 0.4 1.05 1.2 PSAT Saturated Output Power dBm -16 -11 -8 -13 -8 -5 LOLEAK LO Leakage at IF Port (fLO/2) dBm -49 -37 -39 -28 IM REJ Image Rejection at IF Port (fLO/2 - f I/Q)1 dBc 28.5 37 28.5 38 IM3 Third Order Intermodulation Distortion1 dBc 37 56 ZI/Q I/Q Port Input Impedance K Ω 500 1000 500 700 RLLO LO Port Return Loss dB 26 26 RLIF IF Port Return Loss dB 21 21 τ Power Enable Response Time Turn on µsec 15 15 Turn off µsec 13 13 VENABLE Power Enable Control Voltage On V 1.8 5.5 1.8 5.5 Off V 1.0 1.0 California Eastern Laboratories |
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