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Z4 Core exception overview

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Z4 Core exception overview

Z4 Core used on SPC56EL60xx/SPC56xL70xx devices contains many exception sources

and sixteen interrupts to service them. Multiple exception sources can be mapped to one

interrupt handler where few supportive status registers provide flags to find the cause of the

exception in the handler.

Detail list of exception causes and their mapping to interrupt handlers can be found in the Z4

Core Reference Manual. This reference manual is available online at http://www.st.com.

This chapter gives overview simple overview of machine check interrupt that is utilized for

several important fault states of SPC56EL60xx/SPC56xL70xx device.

1.1

Machine check interrupt (IVOR1)

Machine check interrupt is a handler that services multiple fault events that can occur during

runtime code execution.

This interrupt is used to handle various faults generated by peripherals in the

SPC56EL60xx/SPC56xL70xx device, like MPU protection fault, 2bECC error in the Flash or

RAM memory etc. The reason is that most of the faults are signaled back as external bus

error situation during the CPU-Submodule bus transaction.

1.1.1

Machine check registers

Z4 core implements few machine check status registers that are updated upon the

exception event with some constraints stated in the Z4 Core Reference Manual. These

registers are used to find the source of the exception and based on it to decide how to solve

it.

Table 1. Machine check interrupt causes

Interrupt type

Exception conditions

Machine check

–NMI

– ISI, ITLB, Error on first instruction fetch for an exception handler

– Parity Error signaled on cache access

– External bus error

Table 2. Machine check register

Register

Content

MCSR (syndrome register)

Register indicates the source of machine check condition that gives

possibility to differentiate between them

MCAR (address capture)

Register contains for some sort of machine check conditions the

address for which the asynchronous type of the machine check

exception was raised.

Address valid only when MCSR.MAV bit was ‘0’ before the exception,

otherwise MCAR register is not updated.