AN1335 - APPLICATION NOTE

8/10

8.3.3.1 - Software Configuration

; init XTCR

MOV

R3, #0C000h

;XTCR address

MOV

R0, #009Eh

;configuration value

MOV

[R3], R0

; init TSVR

MOV

R3, #0C002h

;register address

MOV

R0, #0000h

;start value

MOV

[R3], R0

; init TEVR

MOV

R3, #0C004h

;register address

MOV

R0, #000Fh

;end value

MOV

[R3], R0

; run Xtimer by XTCR

MOV

R3, #0C000h

MOV

R0, #009Fh

MOV

[R3], R0

Note : bit : "interrupt enable" in XTCR shall be set to enable th esignal on Xtimer output pin (X_ADC_INJ).

8.3.3.2 - Hardware Configuration

In practice, the falling edge of the X_ADC_INJ signal must be delayed up to 8 CPU clock cycles. The

following figure shows the external circuit that have to be added:

8.4 - XPWM

XPWM are identical to the one in ST10 peripheral address range.

The differences to the user are due to the fact they are not bit addressable and that all the associated

interrupt requests have been ORed on a single interrupt node.

Figure 1 : External Connection for ADC Channel Injection

Input

Latch

XTIMER

Clock

P7.7/CC31

X_ADC_INJ

CAPCOM2 UNIT

C

R

Output trigger for ADC

channel injection

Typical value:

R = 10K

Ω C = 47pF at 40MHz