AN3316 datasheet(31/42 Pages) STMICROELECTRONICS

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AN3316

Device modes

Doc ID 18232 Rev 2

31/42

For the HW steps, refer to Section : Common HW aspects. Now see in details the operation

done for each phase:

RUN0 mode:

Mode config in STDBY:

STANDBY mode, by default has already following configuration:

–

CFLASH/DFLASH in Power Down

–XTAL OFF

–

Sysclk OFF

So, the only sw configurations to perform are:

ME_ STANDBY_MC.FIRCON = 0 (turn-off the FIRC)

CGM_ LPRC.LPRCON_STDBY = 1 (turn-on the LPRC in STANDBY)

Moreover, it needs that all peripherals are clock-gated, otherwise, STANDBY mode is

not entered properly, so:

ME_ RUN_LPx.STANDBY = 0 (all low power peripheral configuration registers used

should have STANDBY disabled)

STDBY Boot config:

RGM_STDBY.BOOT_FROM_BKP_RAM = 1 (boot from SRAM on STANDBY exit)

ME_DRUN_MC.CFLAON = 1

(code Flash in Power-Down)

PCU_PCONF2.STDBY0 = 0

(SRAM 24K powered-off)

with these settings, after exiting from STANDBY, device enters in DRUN booting from

SRAM (8K backup) with CFLASH in Power-Down, minimizing consumption

API config:

This step should configure the API to generate a periodic wakeup to exit device from

STANDBY

Request transition to RUN0 mode:

in case of RUN0

 STANDBY transition, these two register writing should be done:

ME.MCTL.R = 0xD0005AF0

ME.MCTL.R = 0xD000A50F

RUN0

 STANDBY mode:

Once a valid mode transition request is detected, the transition starts. Here, device

switchs-off core and all the modules/peripherals that belong to Power-Domain #1. Only

Power-Domain #2 is maintained on.

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