JTAG Data Communication (JDC)

AN4623

6/16

DocID027178 Rev 1

JOUT JTAG register field descriptions:

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JOUT_IPS: Data value from JOUT_IPS register [32 bit]

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JIN_RDY: State of JIN_RDY bit from MSR

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JOUT_RDY: State of JOUT_RDY bit from MSR

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JTAG input data register (JIN): Data is written to the JIN register via JTAG during

execution of the JIN_WRITE JTAG instruction. The JIN data is later captured in the

JIN_IPS register to be read via IPS. This register is reset by system destructive reset

and JTAG reset.

JIN JTAG register field descriptions:

•

JIN Data: Contains data to be captured in JIN_IPS register upon exit of Update-DR

state when executing WRITE_JIN JTAG instruction.

1.5

Functional description

The JDC module provides the ability to shift in data via the JTAG port and capture that data

into a memory mapped register that can be accessed via IPS. It also provides the ability to

capture data written to a memory mapped register into a JTAG shift register for output via

the JTAG port. An overview of the module functionality is described below.

A software writes to the JOUT_IPS register sets the JOUT_RDY flag bit, that indicates new

data is available to be read from the JOUT register via the JTAG port. The state of the

JOUT_RDY bit is reflected in the MSR and also ported out to the JOUT register. A JTAG

read of the JOUT register via execution of the JOUT_READ instruction with a JOUT_RDY

bit whose value is logic 1 indicates the register contains new data. The JOUT_RDY flag bit

is cleared upon exit of the Capture-DR JTAG state during execution of the JOUT_READ

instruction. Clearing the JOUT_RDY bit indicates to software that a new data value can be

written to the JOUT_IPS register.

A JTAG writes to the JIN register via execution of the JIN_READ JTAG instruction updates

the contents of the JIN_IPS register upon exit of the Update-DR state. An update of the

JIN_IPS register sets the JIN_RDY flag bit, that indicates new data is available to be read

via IPS. The state of the JIN_RDY bit is reflected in the MSR register and also ported out to

the JOUT register. The JIN_RDY flag bit is cleared upon software read of the JIN_IPS

register. A JTAG reads of the JOUT register with a JIN_RDY value of logic 0 indicates that

new data can be written to the JIN register.

1.6

JTAG register access

The JDC block implements the IEEE 1149.1-2001 defined instructions listed in Table 1. This

section gives an overview of each instruction; refer to the IEEE 1149.1-2001 standard for

more details. All undefined opcodes are reserved.