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TN0436 Datasheet(PDF) 6 Page - STMicroelectronics

Part # TN0436
Description  This document describes the differences between
PDF  10 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

TN0436 Datasheet(HTML) 6 Page - STMicroelectronics

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TN0436
Differences cut1 and cut2
Doc ID 18327 Rev 2
6/10
2.2
Feature enhancements
The list below shows feature enhancements for cut2.
●
Nexus - NXSS
●
Nexus - RDY PIN
●
Nexus – DDR mode – I/O timing
●
DSPI enhanced version
●
CRC Unit - support for additional polynominal
●
AIPS MPROT - enhanced protection features
●
MC_RGM - destructive reset can be triggered by software
●
SSCM - easier access to NVM calibration data
●
Selftest - reduction of execution time
2.2.1
Nexus - NXSS
The Nexus Crossbar Slave Port Data Trace Module for System SRAM allows to trace all
DMA/SRAM accesses.
2.2.2
Nexus - RDY PIN
To increase the transfer rate of the IEEE 1149.1 port, an additional pin has been
implemented to signal when data are ready to be transferred to and from NRRs. This may
eliminate the need to poll NRRs for status information for synchronization purposes. This
capability becomes especially important when performing read/write access transfers to
different speed target memories.
This functionality is only available on BGA257 package (ball K3). RDY is muxed with GPIO
(GPIO is default out of reset).
2.2.3
Nexus - DDR mode – I/O timing
The I/O timing has been changed so that the MDO / MSEO outputs are valid during the
MCKO rising and falling edges.
2.2.4
DSPI - enhanced version
Support higher net through put in slave mode by reducing required dead cycles in back to
back operation.
2.2.5
CRC Unit - support for additional polynominal
An additional 8-bit CRC polynomial has been implemented. The bit field 28:29 of the register
CRC_CFG for each context selects the polynomial preserving compatibility with previous
versions of this IP used on cut1.
2.2.6
AIPS MPROT - enhanced protection features
The default reset MPROT (Master Protection) configuration for each AIPS bridge is
determined via the aips_rstcfg vector which has been changed.



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