UPD17068 datasheet(39/341 Pages) NEC

39 / 341 page

µPD17068

4.2

CONFIGURATION AND FUNCTIONS OF DATA MEMORY

Fig. 4-2 shows the configuration of the data memory.

As shown in Fig. 4-2, the data memory is divided into banks. Each bank consists of 128 nibbles made up

of row addresses 0H to 7H by column addresses 0H to FH.

The data memory is divided into the functional blocks described in Sections 4.2.1 through 4.2.6.

By using data memory manipulation instructions, 4-bit operations, comparison, decision, and transfer

operation can be performed for the data memory.

Table 4-1 indicates the data memory manipulation instructions.

4.2.1

System Register (SYSREG)

A system register is allocated at addresses 74H-7FH.

A system register is allocated, independently of the banks; each bank contains the same system register

at addresses 74H-7FH.

See Chapter 5 for details.

4.2.2

Data Buffer (DBF)

A data buffer is allocated at addresses 0CH-0FH of BANK0.

See Chapter 9 for details.

4.2.3

VRAM (Video RAM) for the IDC

Addresses 00H-3FH of BANK2 of the data memory can also be used as a VRAM for the IDC.

Fig. 4-3 shows the configuration of the VRAM. The VRAM consists of VRAMBANK0-VRAMBANKD, that is,

672

× 16 bits. A VRAMBANK can be specified using the VRAM select register at addresses 73H of BANK2.

This area is used when the VRAMSEL flag (RF: address 33H, bit 3) is set to 1. When this area is not used

as the VRAM, this area can be used as an ordinary RAM.

See Chapter 16 for details.

4.2.4

Port Register

A port register is allocated at addresses 70H-73H of BANK0 and BANK1, and at addresses 6FH and 70H-

72H of BANK2.

See Chapter 10 for details.

4.2.5

General-Purpose Data memory

The general-purpose data memory consists of the data memory other than the system registers and port

registers.

The general-purpose data memory is made up of 335 nibbles; 112 nibbles of each of BANK0 and BANK1,

and 111 nibbles of BANK2.

4.2.6

Unmounted Data Memory

The data memory at addresses 30H-3FH of BANK2 and some portion of the port registers are not allocated

for any purpose.

For details of the unmounted data memory area, see Section 4.4.2 and Chapter 10.

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