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PA1981 Datasheet(PDF) 3 Page - Renesas Technology Corp |
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PA1981 Datasheet(HTML) 3 Page - Renesas Technology Corp |
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3 / 6 page ![]() The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. INTEGRATED LOAD SWITCH µ PA1981 N-CHANNEL/P-CHANNEL MOS FET PAIR FOR LOAD SWITCH DATA SHEET Document No. G17263EJ1V0DS00 (1st edition) Date Published July 2004 NS CP(K) Printed in Japan 2004 DESCRIPTION The µ PA1981 is a N-Channel/P-Channel MOS FET pair for compact power management in portable electronic equipment where 2.5 to 8 V input and 2.8 A output current capability are needed. This load switch integrated a small N-Channel MOS FET (Q1), which drives a large P-Channel MOS FET (Q2) in one tiny package (SC-95). FEATURES • VS2D21 = 0.2 V MAX. (VS2S1 = 5.0 V, ID2 = −2.8 A, RD2S2(on)1 = 70 mΩ) • VS2D22 = 0.2 V MAX. (VS2S1 = 2.5 V, ID2 = −1.9 A, RD2S2(on)2 = 105 mΩ) ORDERING INFORMATION PART NUMBER PACKAGE µ PA1981TE SC-95 (Mini Mold Thin Type) Marking: TZ ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Source2 to Source1 Input Voltage Range VS2S1 2.5 to 8.0 V Gate1 to Source1 On Voltage Range VG1S1 1.5 to 7.0 V Drain2 Current (DC) Note1 ID2(DC) −2.8 A Drain2 Current (pulse) Note2 ID2(pulse) −10.0 A Total Power Dissipation Note1 PT 1.0 W Channel Temperature Tch 150 °C Storage Temperature Tstg −55 to +150 °C Notes 1. Mounted on FR-4 Board of 2500 mm 2 x 1.6 mm, t ≤ 5 sec 2. PW ≤ 10 µs, Duty Cycle ≤ 1% Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. PACKAGE DRAWING (Unit: mm) 0.65 0.9 to 1.1 0 to 0.1 0.16 +0.1 –0.06 0.95 1.9 2.9 ±0.2 0.32 +0.1 –0.05 0.95 PIN CONNECTION (Top View) 12 3 65 4 1. S1(Q1) 2. D2(Q2) 3. D2(Q2) 4. S2(Q2) 5. G1(Q1) 6. G2/D1 |
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