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AN576 Datasheet(PDF) 2 Page - STMicroelectronics

Part # AN576
Description  PCB LAYOUT OPTIMISATION
PDF  6 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN576 Datasheet(HTML) 2 Page - STMicroelectronics

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Figure 2. Recommended protection location
In this case the current due to the clamping phase of P remains located in the disturbance area and the
track B is not affected.
To summarize, it is recommended that the protection device is located as close as possible the distur-
bance source. For example, all the lines coming into the board ought to be protected close to the connec-
tor.
INFLUENCE OF THE PCB LAYOUT ON THE ESD PROTECTION
These days, printed circuit boards are often auto-routed by computer aided design and the track lengths
are not optimized.
Figure 3. Non-optimized LAYOUT for ESD
Figure 3 shows the classical non-optimized layout. When a surge occurs the protection device P acts and
there is a clamping voltage VCL across it. Due to the fast rise time of the ESD overvoltage there is a high
di/dt between the points A and B. This di/dt generates, in the parasitic inductances located between A and
P and between B and P, overvoltages up to several hundred volts. So the applied voltage V across the
device to be protected is the sum of the clamping voltage and the voltage across the parasitic inductance:
thus the sensitive module is not protected.
P
I
Track B
Track A
V
CL
DEVICE
TO BE
PROTECTED
DISTURBANCE
SOURCE
DISTURBANCE
SOURCE
A
P
U
B
DEVICE
TO BE
PROTECTED



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