Synchronous buck converter description

AN4150

4/20

Doc ID 023526 Rev 1

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Synchronous buck converter description

1.1

Topology and theory of operation

The platform used for the gate current characterization is a single-phase synchronous buck

converter. In Figure 1, the basic schematic is depicted, where S1 is the control FET (or high-

side FET) and S2 is the synchronous FET (or low-side FET). In the same image, it is also

shown that the Power MOSFET gate signals are provided by the “control unit” in a

synchronous way: S1 and S2 cannot be in an ON state simultaneously, avoiding the creation

conduction), generating a spurious power dissipation worsening overall efficiency. L and CO

form the output filter (low-pass filter), which generates a DC voltage from a square-wave

signal on the low-side drain (so-called phase node).

The synchronous buck converter is a closed-loop topology as the output voltage is

compared firstly with a reference voltage, producing an error signal; this voltage is then

compared to a sawtooth signal, at the desired switching frequency (fSW) (integrated in the

control unit) to switch on and off the Power MOSFETs. In this way, the output voltage is

regulated when line or load changes occur.

Together with the output voltage regulation, the control unit provides complete logic control

and protection (overcurrent, overvoltage, undervoltage, etc.…).

When S1 is on, the current in the output coil increases linearly:

body-drain diode of S2 till its gate-source signal becomes high. Therefore, the load current

signals are low and the body-drain diode is forward-biased, allowing the load current flow.

Figure 1.

Single phase synchronous buck converter topology

Control Unit

S2

S1

L

Co

Vin

dead me

dead me

S1 gate

signal

S2 gate

signal

AM14938v1

dl

dt

-----

V

IN

V

OUT

–

L

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