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GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124...

1.7.2 PWM Mode

The OCF1 bit cannot be set by hardware in PWM mode, but the OCF2 bit is set every time the

counter matches the value in the OC2R register. This can generate an interrupt if the OCIE is

set or if the OCIE is reset and OC2IE is set. This interrupt will help any application where pulse

widths or periods need to be changed interactively.

1.8 A/D CONVERTER (ADC)

A new A/D converter with the following main features has been added:

– 16 channels,

– 10-bit resolution,

– 4 MHz maximum frequency (ADC clock),

– 8 ADC clock cycles for sampling time,

– 20 ADC clock cycle for conversion time,

– Zero input reading 0x0000,

– Full scale reading 0xFFC0,

– Absolute accuracy is ± 4 LSBs.

This new A/D converter has the same architecture as the previous one. It still supports the an-

alog watchdog feature, but now it uses only 2 of the 16 channels. These 2 channels are con-

tiguous and channel addresses can be selected by software. With the previous solution using

two ADC cells, four analog watchdog channels were available but at fixed channel addresses,

channels 6 and 7.

Refer to the updated ST92F124/F150/F250 Datasheet for the description of the new A/D Con-

verter.

1.9 I²C

1.10 I²C IERRP BIT RESET

On the ST92F124/F150/F250 I²C, the IERRP (I2CISR) bit can be reset by software even if one

of the following flags is set:

– SCLF, ADDTX, AF, STOPF, ARLO and BERR in the I2CSR2 register

– SB bit in the I2CSR1 Register

It is not true for the ST92F120 I²C: the IERRP bit cannot be reset by software if one these flags

is set. For this reason, on the ST92F120, the corresponding interrupt routine (entered fol-

lowing a first event) is re-entered immediately if another event occurred during the first routine

execution.