8

LTC1821

Table 1

CONTROL INPUTS

CLR

WR

LD

REGISTER OPERATION

0

X

X

Reset Input and DAC Register to All 0s for LTC1821 and Midscale for LTC1821-1 (Asynchronous Operation)

1

0

0

Write Input Register with All 16 Data Bits

1

1

1

Load DAC Register with the Contents of the Input Register

1

0

1

Input and DAC Register Are Transparent

1

CLK = LD and WR Tied Together. The 16 Data Bits Are Written Into the Input Register on the Falling Edge of the CLK and Then

Loaded Into the DAC Register on the Rising Edge of the CLK

1

1

0

No Register Operation

TRUTH TABLE

96k

12k

12k

96k

48k

96k

48k

96k

DECODER

D15

(MSB)

D13

D14

D15

D12

D11

D0

(LSB)

LOAD

REF

DNC*

CLR

7

DGND

*CONNECTED INTERNALLY.

DO NOT CONNECT EXTERNAL

CIRCUITRY TO THESE PINS

1

1821 BD

DAC REGISTER

48k

48k

48k

48k

48k

48k

48k

12k

23

2

R1 10

8

LD

24

25

D14

26

D4

36

D3

3

D2

4

D0

6

D1

5

WR

18

NC

22

13

DNC*

19

DNC*

21

15

14

20

AGNDS

16

AGNDF

17

12

11

• • •

12k

WR

INPUT REGISTER

• • • •

RST

RST

BLOCK DIAGRA