6/7

STR71x MEMORY MAPPING AND DEVELOPMENT TOOLSET

3 SOFTWARE REMAPPING

On power-up, an aliased copy of either ROM or RAM is located at address 0x0. This depends

on the boot mode and the user application. But in some applications it may be necessary to

change the memory map after reset.

This is because, having ROM starting at address 0x0 slows down the handling of processor

exceptions through the exception table. Also, the vector table cannot be overwritten if it is on

ROM. On the other hand, if RAM is mapped to address 0x0 after reset, there will be no valid

instruction in the reset vector, unless you use debug mode.

You can get around this issue by resorting to memory remapping. After remapping, the vector

table must be copied to memory address 0x0.

Remapping is done by changing the Boot[1:0] bits in the boot configuration register (BOOT-

CONF). This code is executed by the ARM7TDMI in SVC mode.

The following example shows the code for remapping the RAM to 0x0 and copying the vector

table to memory address 0x0.

IF :DEF: remap_flash

MOV r0, #FLASH_mask

LDR pc, =next

ENDIF

IF :DEF: remap_ram

; Copying the vector table into RAM

LDR r0, = vector_begin

; r0 is start address from which to copy

LDR r2, =0x0fffffff

LDR r3, =vector_end

AND r3, r2, r3

; r3 is number of byte to be copy

LDR r1, = RAM_base

; r1 is start address where to copy

copy

LDR r2, [r0], #4

; Read a word from the source

STR r2, [r1], #4

; Copy the word to destination

SUBS r3, r3, #4

; Decrement number of word to copy

BNE copy

; Branch to copy if r5 not equal to 0

MOV r0, #RAM_mask

LDR pc, =next

ENDIF

IF :DEF: remap_ext

MOV r0, #EXTMEM_mask

LDR pc, =next

ENDIF

next

LDR r1, =CPM_base_addr

; r0= CPM base address

LDRH r2, [r1, #BOOTCONF_off_addr] ; Read BOOTCONF Register

BIC r2, r2, #0x03

; Reset the two lsb bits of BOOTCONF Reg.

ORR r2, r2, r0

; Change the two LSB bits of BOOTCONF Reg.

STRH r2, [r1, #BOOTCONF_off_addr] ; Write BOOTCONF Register