I2C emulation

AN2038

4/23

A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition.

A LOW to HIGH transition on the SDA line while SCL is HIGH indicates a STOP condition

(see Figure 3). START and STOP conditions are always generated by the master. The bus is

considered to be busy after the START condition. The bus is considered to be free again

after the STOP condition.

Figure 3.

Start/Stop condition

Every byte put on the SDA line must be 8 bits long. The number of bytes that can be

transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit.

Data is transferred with the most significant bit (MSB) first (see Figure 4).

Figure 4.

Data Transfer

The acknowledge clock pulse is generated by the master. The transmitter releases the SDA

line (HIGH) during the acknowledge clock pulse and the receiver must pull down the SDA

line during the acknowledge clock pulse so that it remains stable LOW during the HIGH

period of this clock pulse.

Data transfers follow the format shown in Figure 5: after the START condition (S), a slave

address is sent. This address is 7 bits long followed by an eighth bit which is a data direction

bit (R/W) - a 'zero' indicates a transmission (WRITE), a 'one' indicates a request for data

(READ). A data transfer is always terminated by a STOP condition (P) generated by the

master.

Stop

Start

SCL

SDA

12

7

8

12

7

8

MSB

LSB

MSB

LSB

Start

Stop

ACK

ACK

SDA

SCL

First byte

Second byte