6

LTC4301

4301fb

OPERATIO

There is a finite high to low propagation delay through the

connection circuitry for falling waveforms. Figure 2 shows

the falling edge waveforms for the same pull-up resistors

and equivalent capacitance conditions as used in Figure 1.

An external N-channel MOSFET device pulls down the

voltage on the side with 55pF capacitance; LTC4301 pulls

down the voltage on the opposite side with a delay of 60ns.

This delay is always positive and is a function of supply

voltage, temperature and the pull-up resistors and equiva-

lent bus capacitances on both sides of the bus. The Typical

Performance Characteristics section shows high to low

propagation delay as a function of temperature and volt-

equivalent capacitance on both sides of the part. Larger

output capacitances translate to longer delays (up to

150ns). Users must quantify the difference in propagation

times for a rising edge versus a falling edge in their

systems and adjust setup and hold times accordingly.

Figure 2. Input-Output Connection

High to Low Propagation Delay

Ready Digital Output

This pin provides a digital flag which is low when either CS

is high or the start-up sequence described earlier in this

section has not been completed. READY goes high when

CS is low and start-up is complete. The pin is driven by an

open-drain pull-down capable of sinking 3mA while hold-

provide the pull-up.

Connection Sense

When the CS pin is driven above 1.4V with respect to the

LTC4301’s ground, the backplane side is disconnected

from the card side and the READY pin is internally pulled

low. When the pin voltage is low, the part waits for data

transactions on both the backplane and card sides to be

complete (as described in the Start-Up section) before

reconnecting the two sides. At this time the internal

pulldown on READY releases.

4301 F02

INPUT

SIDE

55pF

OUTPUT

SIDE

20pF

1V/DIV

20ns/DIV