BLDC motor control using ST7FMC

AN2267

6/19

Figure 6.

Motor Control Macro cell - BLDC motor control configuration

A PWM output is generated as a result of comparison between this carrier and a compare

register (MCPUH:MCPUL) that carries pulse width (duty cycle) information. This PWM

signal is directed to one of the six inverter switches by a CHANNEL MANAGER that acts as

a traffic diverter on the PWM output. The channel manager also selects a complementary

switch, as programmed by the user, which together with the switch receiving PWM will force

current into the motor windings. Based on the motor terminal voltages or Hall sensor

outputs, an analog block identifies the motor phase BEMF Z events and captures the

contents of MTIM timer into MZREG and the previous value of MZREG into MZPRV and this

cycle repeats all over again.

MTIM[8-bit Up Counter]

C

A

B

HV

D

Q

CP

Mi crocontroll er

+

V

RE

F

ZV D b it

-

MCCFI

MCO0

MCO2

MCO4

MCO1

MCO3

MCO5

HDM

IS

Board + Motor

VR2-0

MCI C

MCI A

MCI B

MWGHT Reg [a

n+

1

]

A x B/ 256

Fcpu

D

S

ST3-0 bits

4

DCB bit

SDM

n

bit

SWAbit

MDREG Reg [ D

n

]

Com pare

Compare

MCOMP Reg [C

Z

H

1 / 2

Ratio

1 / 2

MZREG

MTIM

SA3-0 &

12- bit P W M ge nera tor

SQ

R

NMCES

+1

-1

Z

cl r

x6

x6

ck

C

S,H

D

S,H

E

6

6

8

8

8

8

1

Filt er/ PWM

1

1/ 128

OT1-0 bits

n

n-1

R

+

R

-

R

-/+

CL

3

SR bit

+

-

or

or

or

or

1

2

Filte r / D

Filt e r / C

1 /20

1 / 4

A

CPB

REO bi t

C

S,H

< 55h?

= FFh?

CPB

n

bit

1

0

SWAbit

(V)

R

1ext

R

2ext

V

DD

(I)

MCPWMU

MCPWMV

MCPWMW

MCVREF

SPLG

EF [2 : 0]

EF [2 :0 ]

PZ b it

SZ

n

Compare

bit

Z

S

8

2

6

MCAOP

MCAON

MCCREF

MCPWMU/V/ W

+

-

CL

XT16 bi t

MCAOZ

CFAVbit