AN2442

DMA unit

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1.4

DMA transfer properties

A DMA transfer is characterized by the following properties:

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DMA Channel

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Source and destination addresses

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Source and destination data width

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Flow control

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Transfer type

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Transfer size (only when DMAC is the flow controller)

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Source / destination burst size

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Source / destination address incrementing or non-incrementing

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Terminal count interrupt generation

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Next linked list item address

In the following paragraphs, a detailed description of each DMA transfer property is provided.

1.4.1

DMA channel

A DMA channel needs to be allocated by the user (8 channels are available) for the DMA

request. The choice of the channel depends on the required priority (0 to 7) and on the

availability of the channel (not already allocated to another request).

1.4.2

Source and destination addresses

A DMA transfer is defined by a source address and a destination address. Both the source and

destination should be in the AHB or APB memory ranges.

1.4.3

Source and destination data width

Data width for source and destination can be defined as:

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Byte

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Half word (16-bit)

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Word (32-bits)

1.4.4

Flow control

The flow controller is the unit that controls the data transfer length and which is responsible for

stopping the DMA transfer.

The flow controller can be either the DMAC or the peripheral.

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With DMAC as flow controller:

In this case, it is necessary to define the transfer size value.

When a DMA request is served, the transfer size value decreases by the amount of

transferred data (depending of the type of request: burst or single).

When the transfer size value reaches 0, the DMA transfer is then finished and the DMA

channel is disabled in case of no next linked list item, otherwise a new linked list descriptor

will be fetched from SRAM into DMA registers.

For further details about linked lists, refer to Section 1.4.10.

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With the peripheral as flow controller: