December 2009

Doc ID 14454 Rev 1

1/12

AN2715

Application note

IBIS models for signal integrity

simulation of SPEAr600 applications

Introduction

This application note is intended for hardware developers that are using the SPEAr600

embedded MPU in their target design.

The IBIS models are mandatory to run signal integrity simulation in the application PCB.

PCB simulation is very important to make sure that the layout of the PCB does not introduce

any functional problems or timing marginality in high speed interfaces like DDR2 and

Ethernet.

The IBIS models provided for SPEAr600 are organized in a model library containing several

models for each I/O pin (or for a functional group of I/Os). Each I/O pin or functional group of

I/O has a set of models; each model corresponds to a certain operating mode of the I/O

pads.

The operating modes are programmable and are defined by a proper setting of two

registers, one in the miscellaneous register block and the other one in the memory controller

block of the SPEAr600 device (for more details please refer to the miscellaneous registers

and memory controller sections of the SPEAr600 user manual).

This document explains how to select the correct model from the library sp600_v13.ibs after

reading the register settings or knowing the operating mode from the SPEAr600 user

manual.

Note:

The registers referred to in this document are described in detail in the SPEAr600 user

manual.

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