Measuring the DE signal switching time using the two methods

AN3070

8/12

Doc ID 16312 Rev 1

3

Measuring the DE signal switching time using the

two methods

This section gives some DE timing measurements using the two previously described

methods.

The timing to be measured is the time interval between the end of the stop bit of the last byte

and the falling edge of the DE signal. It is measured in CPU clock cycles (refer to Figure 4).

Figure 4.

Zoom in DE signal switching period

The MCO pin (PA8) is used to output the system clock (CPU clock) in order to measure in

CPU cycles the time taken by the DE signal to switch to the low level.

The end of the stop bit is evaluated by measuring the number of CPU clock cycles during a

bit time.

This application note is released with two examples of firmware that implement the two

previously described methods. Both examples describe the same sequence: drive PC6 high

(DE signal), send a buffer of 4 bytes and then drive PC6 low.

The user can select the CPU frequency (72 MHz or 24 MHz) by commenting/uncommenting

the following define in the main.c files:

#define HCLK_FREQ_72MHz

72 MHz is selected by default.

3.1

Measuring the DE signal switching time

This timing depends on different factors such as the compiler used, the level of optimization

or the CPU frequency.

The examples are built with two compilers: Keil™ 4.00 and IAR 5.40.

They implement two optimization modes: low optimization and high optimization on timing.

The baud rate for transmission is 230400 baud (bit time = 4.34 µs), 1 stop bit.