Software

UM0244

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4

Software

The FlashLINK cable assembly is driven by the software development tool CAPS (available

at no charge from www.st.com/mcu). With this tool you define the pin functions, memory

map, and configuration of STR91x devices, add microcontroller firmware to be programmed

into Flash memory, then generate a single file to program into the device (an object file with

the filename extension *.obj). CAPS will then use the FlashLINK cable assembly to program

this object file into the STR91x device. Other operations include erase, verify, upload, and

blank check. See the CAPS User Manual for more detail.

Note:

Be sure to use the latest version of CAPS. Updates are available from www.st.com/mcu.

4.1

Diagnostic tests

CAPS also performs some diagnostic tests for the PC parallel port and FlashLINK cable

assembly.

4.1.1

Loop test

Should be run first to test basic operation of the PC parallel port and the FlashLINK cable

assembly. “LoopTest” will wrap FlashLINK signal outputs back into FlashLINK signal inputs

for signal path verification.

4.1.2

Connect test

Is optional to test system performance and check the JTAG signal path all the way through

the target circuit board including STR91x device.

To run these tests, install and run CAPS on your PC or laptop:

1.

Connect the six foot long DB-25 cable to your PC parallel port on one side, and to the

FlashLINK Adaptor on the other side.

2.

Click mouse on the “Program Device” box at the bottom-left of the CAPS main flow

diagram.

3.

Select single or multiple JTAG devices depending on your target configuration (single is

most common), then click on the Hardware Setup (“HW Setup”) button at the lower part

of the JTAG Operations window.

For “LoopTest”:

1.

Connect the small loop test adaptor cable (not the flying lead cable) to the 14-pin

connector on the FlashLINK Adaptor.

2.

connect the black lead of the loop test connector to ground.

3.

In the “HW Setup” dialog screen click the “Loop Test” button to run the test. If it fails, be

port is enabled.

For “Connect Test”: