UPD70741 datasheet(19/112 Pages) NEC

19 / 112 page

µPD70741

3.3.2 System register set

System registers are used to control the state of the CPU and store interrupt information.

Table 3-2. System Register Numbers

No.

Use

Explanation

EIPC

Registers for saving the current

Retain the contents of PC and PSW if an exception or

status upon the occurrence of an

interrupt occurs. Note, however, that there is only one

exception or interrupt

pair of these registers.

EIPSW

When multiple interrupts are allowed, therefore, the

contents of the registers must be saved by the program.

FEPC

Registers for saving the current

Retain the contents of PC and PSW if an

status upon the occurrence of an

NMI or double exception occurs.

FEPSW

NMI or double exception

ECR

Exception source register

Stores the source of an exception, maskable interrupt, or

NMI. The upper 16 bits of this register are called

"FECC" and set to the exception code of an NMI/double

exception. The lower 16 bits are called "EICC" and set

to the exception code of an exception/interrupt.

PSW

Program status word

The program status word is a set of flags indicating the

state of the program (result of executing an instruction)

and the state of the CPU.

PIR

Processor ID register

Used to identify a CPU type number.

TKCW

Task control word

Used to control a floating-point operation.

8-23

Reserved

CHCW

Cache control word

Used to control the built-in instruction cache.

ADTRE

Address trap register

Stores the address used to detect an address match with

PC, and to generate an address trap.

26-31

Reserved

Read and write operations made to these system registers can be performed using the system register load/store

instructions (LDSR and STSR) with the system register numbers specified.

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