System overview

UM1546

8/17

Doc ID 023229 Rev 1

Figure 5.

RC5 idle time

2.1.3

RC5 frame reading mechanism

RC5 decoding algorithm features:

●

Adaptive timing takes care of variations in transmitter bit period within the standard

range specified in Table 1.

●

Algorithm synchronizes sampling time after every bit to ensure robust decoding

performance.

●

Uses one external interrupt and one hardware timer to efficiently decode received data

on the fly.

The RC5 decoded data has the inherent property of changing its logic state at the middle of

every bit transmitted, as it is Manchester format. This state change can be used to

synchronize the sampling of the RC5 data output line connected to the microcontroller for

robust decoding performance irrespective of timing variations at the receiver, as well as the

transmitter side. Figure 4 highlights the decoding algorithm used in this application.

Table 1.

RC5 timings

Description

Min.

Typical

Max.

Units

RC5 half bit period

640

899

1140

µs

RC5 full bit period

1340

1778

2220

µs

RC5 message

time

23.644

24.889

26.133

ms

RC5 message

repetition time

108.089

113.778

119.467

ms

Carrier pulse bit

time

27.233

27.778

28.345

µs

AM12344v1

14 bits

Frame 1

14 bits

Frame 2

50 bits

Idle time

64 bits = 113.788 ms