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LT1572CS Datasheet(PDF) 8 Page - Linear Technology |
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LT1572CS Datasheet(HTML) 8 Page - Linear Technology |
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8 / 12 page ![]() 8 LT1572 OPERATIO to the comparator input. The LT1572 will then regulate the value of the flyback pulse with respect to the supply voltage.1 This flyback pulse is directly proportional to output voltage in the traditional transformer coupled flyback topology regulator. By regulating the amplitude of the flyback pulse, the output voltage can be regulated with no direct connection between input and output. The output is fully floating up to the breakdown voltage of the trans- former windings. Multiple floating outputs are easily ob- tained with additional windings. A special delay network inside the LT1572 ignores the leakage inductance spike at the leading edge of the flyback pulse to improve output regulation. The error signal developed at the comparator input is brought out externally. This pin (VC) has four different functions. It is used for frequency compensation, current limit adjustment, soft starting, and total regulator shut- down. During normal regulator operation this pin sits at a voltage between 0.9V (low output current) and 2.0V (high output current). The error amplifiers are current output (gm) types, so this voltage can be externally clamped for adjusting current limit. Likewise, a capacitor coupled external clamp will provide soft start. Switch duty cycle goes to zero if the VC pin is pulled to ground through a diode, placing the LT1572 in an idle mode. Pulling the VC pin below 0.15V causes total regulator shutdown, with only 50 µA supply current for shutdown circuitry biasing. See AN19 for full application details. E1 and E2 Pins The LT1572 has the emitters of the power transistor brought out separately from the ground pin. This elimi- nates errors due to ground pin voltage drops and allows the user to reduce switch current limit 2:1 by leaving the second emitter (E2) disconnected. The first emitter (E1) should always be connected to the ground pin. Note that switch “on” resistance doubles when E2 is left open, so efficiency will suffer somewhat when switch currents exceed 300mA. Also, note that chip dissipation will actu- ally increase with E2 open during normal load operation, even though dissipation in current limit mode will de- crease. 1See note under block diagram. Other Application Help More circuits and application help for the LT1572 can be found in the LT1172 data sheet, both in loose form and in the 1994 Linear Databook Volume III. Extensive additional help is contained in Application Note 19. All application circuits using the LT1172 can also use the LT1572 as long as the 20V maximum reverse voltage of the diode is not exceeded. A CAD program called SwitcherCAD is also available. This program can be used with the LT1572 by simply treating the LT1572 as an LT1172 and ignoring the predicted die temperature results obtained from SwitcherCAD itself. Thermal Management Thermal management is particularly important with the LT1572 because both switch and diode power dissipation increase rapidly at low input voltage when using the popular boost topology. Regulator and diode die tempera- ture must be calculated separately because they are not connected to an isothermal plane inside the package. Diode plus regulator thermal resistance is approximately 70 °C/W when the LT1572 is soldered to 1oz copper traces over an internal or backside copper plane using FR4 board material. However, individual calculation of die tempera- ture must take thermal coupling into account. To accom- plish this, thermal resistance is broken into two sections, a common (coupled) section and a second uncoupled section. Die temperatures are calculated from: TREG = TA + PREG (90°C/W) + PDIODE (45°C/W) TDIODE = TA + PDIODE (90°C/W) + PREG (45°C/W) TA = ambient temperature TREG = regulator die temperature TDIODE = diode die temperature PREG = total regulator power dissipation PDIODE = diode power dissipation The following formulas can be used as a rough guide to calculate LT1572 power dissipation. For more details, the reader is referred to Application Note 19 (AN19), “Effi- ciency Calculations” section. |
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