LT1719CS6 datasheet(8/16 Pages) LINER

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LT1719

APPLICATIONS INFORMATION

Figure 2 shows a typical topside layout of the LT1719 on

such a multilayer board. Shown is the topside metal etch

including traces, pin escape vias, and the land pads for an

SO-8 LT1719 and its adjacent X7R 10nF bypass capacitors

in the 1206 case.

than + VS. Therefore, if driven by a standard TTL gate, a

pull-up resistor should be used. Because shutdown is

active high, this resistor adds little power drain during

shutdown.

For applications that do not use the shutdown feature, it

may be helpful to tie the shutdown control to ground

through a 100

Ω resistor rather than directly. This allows

the SHDN pin to be pulled high during debug or in-circuit

test (bed of nails) so that the output node can be wiggled

without damaging the low impedance output driver of the

LT1719.

The shutdown state is not guaranteed to be useful as a

multiplexer. Digital signals can have extremely fast edge

rates that may be enough to momentarily activate the

LT1719 output stage via internal capacitive coupling. No

damage to the LT1719 will result, but this could prove

deleterious to the intended recipient of the signal.

The LT1719 includes a FET pull-up on the shutdown

control pin (see Simplified Schematic) as well as other

internal structures to make the shutdown state current

drain <<1

µA. Shutdown is guaranteed with an open circuit

on the shutdown control pin. When the shutdown control

pin is driven to + VS – 0.5V, the 70kΩ linear region

impedance of the pull-up FET will cause a current flow of

µA (typ) into the +VS pin and out the shutdown pin.

Currents in all other power supply terminals will be <1

µA.

Power Supply Sequencing

The LT1719 is designed to tolerate any power supply

sequencing at system turn-on and power down. In any of

the previously shown power supply configurations, the

various supplies can activate in any order without exces-

sive current drain by the LT1719.

As always, the Absolute Maximum Ratings must not be

exceeded, either on the power supply terminals or the

input terminals. Power supply sequencing problems can

occur when input signals are powered from supplies that

are independent of the LT1719’s supplies. For the com-

parator inputs, the signals should be powered from the

same VCC and VEE supplies as the LT1719. For the shut-

down input, the signal should be powered from the same

+VS as the LT1719.

1719 F02

Figure 2. Typical Topside Metal for Multilayer PCB Layouts

The ground trace from Pin 5 runs under the device up to

the bypass capacitor, shielding the inputs from the

outputs. Note the use of a common via for the LT1719 and

the bypass capacitors, which minimizes interference from

high frequency energy running around the ground plane or

power distribution traces.

The supply bypass should include an adjacent

10nF ceramic capacitor and a 2.2

µF tantalum capacitor no

farther than 5cm away; use more capacitance on + VS if

driving more than 4mA loads. To prevent oscillations, it is

helpful to balance the impedance at the inverting and

noninverting inputs; source impedances should be kept

low, preferably 1k

Ω or less.

The outputs of the LT1719 are capable of very high slew

rates. To prevent overshoot, ringing and other problems

with transmission line effects, keep the output traces

shorter than 10cm, or be sure to terminate the lines to

maintain signal integrity. The LT1719 can drive DC termi-

nations of 200

Ω or more, but lower characteristic imped-

ance traces can be used with series termination or AC

termination topologies.

Shutdown Control

The LT1719 features a shutdown control pin for reduced

quiescent current when the comparator is not needed.

During shutdown, the inputs and the outputs become high

impedances. The LT1719 is enabled when the shutdown

input is pulled low. A logic high disables the comparator.

The logic interface is based on the output power rails, + VS

and GND, with a threshold roughly two diode drops less

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