LTC1196 datasheet(19/28 Pages) LINER

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LTC1196/LTC1198

APPLICATI

I FOR ATIO

CLK. VERROR is proportional to f(“–”) and inversely pro-

portional to fCLK. For a 60Hz signal on the “–” input to

generate a 1/4LSB error (5mV) with the converter running

at CLK = 12MHz, its peak value would have to be 18.7V.

ANALOG INPUTS

Because of the capacitive redistribution A/D conversion

techniques used, the analog inputs of the LTC1196/

LTC1198 have one capacitive switching input current

spike per conversion. These current spikes settle quickly

and do not cause a problem. However, if source resis-

tances larger than 100

Ω are used or if slow settling op

amps drive the inputs, care must be taken to insure that the

transients caused by the current spikes settle completely

before the conversion begins.

“+” Input Settling

The input capacitor of the LTC1196 is switched onto “+”

input at the end of the conversion and samples the input

signal until the conversion begins (see Figure 1). The input

capacitor of the LTC1198 is switched onto “+” input during

the sample phase (tSMPL, see Figure 7). The sample phase

is 2.5 CLK cycles before conversion starts. The voltage on

the “+” input must settle completely within tSMPL for the

LTC1196/LTC1198. Minimizing RSOURCE+ will improve

the input settling time. If a large “+” input source resis-

tance must be used, the sample time can be increased by

allowing more time between conversions for the LTC1196

or by using a slower CLK frequency for the LTC1198.

Figure 7. LTC1198 “+” and “–” Input Settling Windows

CLK

DIN

DOUT

“+” INPUT

“–” INPUT

SAMPLE

HOLD

“+” INPUT MUST

SETTLE DURING

THIS TIME

tSMPL

tCONV

START

SGL/DIFF

DUMMY

DON’T CARE

1ST BIT TEST “–” INPUT MUST

SETTLE DURING THIS TIME

1196/98 F07

ODD/SIGN

DUMMY

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