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LTC1415

APPLICATIONS INFORMATION

circuitry. The reference amplifier gains the voltage at the

VREF pin by 1.638 to create the required internal reference

voltage of 4.096V. This provides buffering between the

VREF pin and the high speed capacitive DAC. The reference

amplifier compensation pin (REFCOMP, Pin 4) must be

bypassed with a capacitor to ground. The reference ampli-

fier is stable with capacitors of 1

µF or greater. For the best

noise performance a 10

µF ceramic or tantalum in parallel

with a 0.1

µF ceramic is recommended.

40k

64k

REFERENCE

AMP

µF

REFCOMP

AGND

VREF

BANDGAP

REFERENCE

2.500V

4.096V

LTC1415

LTC1415 • F08a

Figure 8a. LTC1415 Reference Circuit

µF

ANALOG

INPUT

1415 F08b

LT1019A-2.5

VOUT

VIN

+AIN

–AIN

VREF

LTC1415

AGND

REFCOMP

Figure 8b. Using the LT1019-2.5 as an External Reference

LTC1415

+AIN

DIFFERENTIAL ANALOG INPUT

RANGE = (VREF)(1.638)

–AIN

VREF

REFCOMP

AGND

LTC1415 • F09

µF

LTC1450

12-BIT

RAIL-TO-RAIL DAC

1.25V TO 3V

Figure 9. Driving VREF with a DAC to Adjust Full Scale

bandwidth and settling time of this circuit. A settling time

of 5ms should be allowed for after a reference adjustment.

Differential Inputs

The LTC1415 has a unique differential sample-and-hold

circuit that allows rail-to-rail inputs. The ADC will always

convert the difference of +AIN – (–AIN) independent of the

common mode voltage. The common mode rejection is

constant from DC to 1MHz, see Figure 10a. The only

requirement is that both inputs can not exceed the AVDD

or AGND power supply voltages. Integral nonlinearity

errors (INL) and differential nonlinearity errors (DNL) are

independent of the common mode voltage, however, the

bipolar zero error (BZE) will vary. The change in BZE is

typically less than 0.1% of the common mode voltage.

Differential inputs allow greater flexibility for accepting

different input ranges. Figure 10b shows a circuit that

shifts the input range up in voltage by 200mV. This can be

useful in applications where the amplifier driving the ADC

input is not able to swing all the way to ground, because

of output loading or settling time issues.

Some AC applications may have their performance limited

by distortion. Most circuits exhibit higher distortion when

signals approach the supply or ground. Distortion can be

reduced by reducing the signal amplitude and keeping the

common mode voltage at approximately midsupply. The

circuit of Figure 10c reduces the ADC full scale from

The VREF pin can be driven with a DAC or other means

shown in Figure 9. This is useful in applications where the

peak input signal amplitude may vary. The input span of

the ADC can then be adjusted to match the peak input

signal, maximizing the signal-to-noise ratio. The filtering

of the internal LTC1415 reference amplifier will limit the

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