LTC2428C datasheet(17/28 Pages) LINER

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LTC2424/LTC2428

APPLICATIONS INFORMATION

The device remains in the sleep state until the first rising

edge of SCK is seen while CSADC is LOW. Data is shifted

out the SDO pin on each falling edge of SCK. This enables

external circuitry to latch the output on the rising edge of

SCK. EOC can be latched on the first rising edge of SCK

and the last bit of the conversion result can be latched on

the 24th rising edge of SCK. On the 24th falling edge of

SCK, the device begins a new conversion. SDO goes HIGH

(EOC = 1) indicating a conversion is in progress.

At the conclusion of the data cycle, CSADC may remain

LOW and EOC monitored as an end-of-conversion inter-

rupt. Alternatively, CSADC may be driven HIGH setting

SDO to HI-Z. As described above, CSADC may be pulled

LOW at any time in order to monitor the conversion status.

For each of these operations, CSMUX may be tied to

CSADC without affecting the selected channel.

At the conclusion of the data output cycle, the converter

enters a user transparent calibration cycle prior to actually

performing a conversion on the selected input channel.

This enables a 66ms (for 60Hz notch frequency) look ahead

time for the multiplexer input. Following the data output

cycle, the multiplexer input channel may be selected any

time in this 66ms window by pulling CSADC HIGH and

serial shifting data into the DIN pin, see Figure 14.

While the device is performing the internal calibration, it is

sensitive to ground current disturbances. Error currents

flowing in the ground pin may lead to offset errors. If the

SCK pin is toggling during the calibration, these ground

disturbances will occur. The solution is to either drive the

multiplexer clock input (CLK) separately from the ADC

clock input (SCK), or program the multiplexer in the first

1ms following the data output cycle. The remaining 65ms

may be used to allow the input signal to settle.

Typically, CSADC remains LOW during the data output

state. However, the data output state may be aborted by

pulling CSADC HIGH anytime between the first rising edge

and the 24th falling edge of SCK, see Figure 15. On the

rising edge of CSADC, the device aborts the data output

state and immediately initiates a new conversion. This is

useful for systems not requiring all 24 bits of output data,

aborting an invalid conversion cycle or synchronizing the

start of a conversion.

Internal Serial Clock

This timing mode uses an internal serial clock to shift out

the conversion result and program the multiplexer, see

Figure 16. A CS signal directly drives the CSADC input,

while the inverse of CS drives the CSMUX input. The CS

SCK/CLK

SDO

DIN

CSADC/

CSMUX

VCC

FSSET

CSMUX

CSADC

SCK

CLK

MUXOUT

ADCIN

DIN

ZSSET

GND

SDO

0.1V

TO VCC

CH0

TO CH7

–0.12VREF

TO 1.12VREF

2.7V TO 5.5V

LTC2424/LTC2428

MSB

EXR

SIG

BIT0

LSB

BIT4

BIT19 BIT18

BIT20

BIT21

BIT22

BIT23

24248 F13

= 50Hz REJECTION

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

VCC

TEST EOC

DON’T CARE

Hi-Z

TEST EOC

Hi-Z

TEST EOC

SCK

Figure 13. External Serial Clock Timing Diagram

LTC2428C Datasheet(PDF) 17 Page - Linear Technology

LTC2428C Datasheet(HTML) 17 Page - Linear Technology

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