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LF3304 Datasheet(PDF) 3 Page - LOGIC Devices Incorporated |
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LF3304 Datasheet(HTML) 3 Page - LOGIC Devices Incorporated |
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3 / 12 page  DEVICES INCORPORATED Video Imaging Products 3 LF3304 Dual Line Buffer/FIFO 08/16/2000–LDS.3304-F RWB — Reset Write B See RWA Description. RRB — Reset Read B See RRA description. OEA — Output Enable A When OEA is LOW, AOUT11-0 is enabled for output. When OEA is HIGH, AOUT11-0 is placed in a high- impedence state. OEB — Output Enable B When OEB is LOW, BOUT11-0 is enabled for output. When OEB is HIGH, BOUT11-0 is placed in a high- impedence state. Outputs AOUT11-0 — Data Output A AOUT11-0 is the 12-bit registered data output port. BOUT11-0 — Data Output B BOUT11-0 is the 12-bit registered data output port. FIFO MODE SIGNAL DEFINITIONS Power VCC and GND +3.3 V power supply. All pins must be connected. Clocks WCLKA — Write Clock A Data present on AIN11-0 is written into the LF3304 on the rising edge of WCLKA when the device is configured for writing. RCLKA — Read Clock A Data is read from the LF3304 and presented on the output port (AOUT11-0) after tD has elapsed from the rising edge of RCLKA when the device is configured for reading and the output port is enabled. WCLKA and RCLKA can be tied together and driven by the same external clock or they may be controlled by separate external clocks. WCLKB — Write Clock B Data present on BIN11-0 is written into the LF3304 on the rising edge of WCLKB when the device is configured for writing. RCLKB — Read Clock B Data is read from the LF3304 and presented on the output port (BOUT11-0) after tD has elapsed from the rising edge of RCLKB when the device is configured for reading and the output port is enabled. WCLKB and RCLKB can be tied together and driven by the same external clock or they may be controlled by separate external clocks. Inputs AIN11-0 — Data Input A AIN11-0 is the 12-bit registered data input port. BIN11-0 — Data Input B BIN11-0 is the 12-bit registered data input port. ADDRA — Address A If LDA is LOW, on the rising edge of WCLKA data present on AIN11-0 is written into the PAFA or PAEA register depending on ADDRA (see Table 2). The LSB, AIN0, corresponds to the LSB of PAFA and PAEA registers. The MSB, AIN11, corresponds to the MSB of PAFA andPAEAregisters. ADDRB — Address B If LDB is LOW, on the rising edge of WCLKB data present on BIN11-0 is written into the PAFB or PAEB register depending on ADDRB (see Table 2). The LSB, BIN0, corresponds to the LSB of PAFB and PAEB registers. The MSB, BIN11, corresponds to the MSB of PAFB and PAEB registers. MODE1-0 — Mode Select Themodeselectinputsdeterminethe operating mode of the LF3304 (Table 1) for data being input on the next clock cycle. Whenswitchingbetweenmodes,the internal pipeline latencies of the device mustbeobserved. Afterswitching operatingmodes,eithertheusermust allow enough clock clycles to pass to flush the internal RAM Array or RWx and RRx mustbedrivenLOWtogetherbeforevalid data will appear on the outputs. LENGTH — Non-Flag Pins In FIFO Mode, the unused LENGTH pins (LENGTH11, LENGTH10, LENGTH5, LENGTH4) must be tied LOW. Controls LDA — RAM Array A Load When LDA is LOW, data on AIN11-0 is latched in the LF3304 on the rising edge of WCLKA. TABLE 2. LOADING PROGRAMMABLE FLAG REGISTERS ADDRA ADDRB LDA LDB WCLKA WCLKB Operation 0 x 0 x x PAEA Register 1 x 0 x x PAFA Register x 0 x 0 x PAEB Register x 1 x 0 x PAFB Register |
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